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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 167 of 589
6.4.2 Save/Restore Register 0 (SRR0)
SRR0 is an SPR that is used to save machine state on non-critical interrupts, and to restore machine state
when an rfi is executed. When a non-critical interrupt occurs, SRR0 is set to an address associated with the
process which was executing at the time. When rfi is executed, instruction execution returns to the address in
SRR0.
In general, SRR0 contains the address of the instruction that caused the non-critical interrupt, or the address
of the instruction to return to after a non-critical interrupt is serviced. See the individual descriptions under
Interrupt Definitions on page 175 for an explanation of the precise address recorded in SRR0 for each non-
critical interrupt type.
SRR0 can be written from a GPR using mtspr, and can be read into a GPR using mfspr.
6.4.3 Save/Restore Register 1 (SRR1)
SRR1 is an SPR that is used to save machine state on non-critical interrupts, and to restore machine state
when an rfi is executed. When a non-critical interrupt is taken, the contents of the MSR (prior to the MSR
being cleared by the interrupt) are placed into SRR1. When rfi is executed, the MSR is restored with the
contents of SRR1.
Bits of SRR1 that correspond to reserved bits in the MSR are also reserved.
Programming Note: An MSR bit that is reserved may be altered by rfi, consistent with the
value being restored from SRR1.
SRR1 can be written from a GPR using mtspr, and can be read into a GPR using mfspr.
28:31 Reserved
Figure 6-2. Save/Restore Register 0 (SRR0)
0:29 Return address for non-critical interrupts
30:31 Reserved
0 29 30 31