DTV0–DTV3
Data Cache Transient Victim 0–3
PPC440x5 CPU Core User’s Manual Preliminary
Page 484 of 589
regsumm440core.fm.
September 12, 2002
DTV0–DTV3
SPR 0x394–0x397 Supervisor R/W
See Cache Line Replacement Policy on page 96.
Figure 10-19. Data Cache Transient Victim Registers (DTV0–DTV3)
0:7 VNDXA
Victim Index A (for cache lines with EA[25:26] =
0b00)
For all victim index fields, the number of bits used
to select the cache way for replacement depends
on the implemented cache size. See Table 4-3, on
page -98
for more information.
8:15 VNDXB
Victim Index B (for cache lines with EA[25:26] =
0b01)
16:23 VNDXC
Victim Index C (for cache lines with EA[25:26] =
0b10)
24:31
VNDXD
Victim Index D (for cache lines with EA[25:26] =
0b11)
0 7 8 1516 2324 31
VNDXA
VNDXC
VNDXB
VNDXD