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lhaux
Load Halfword Algebraic with Update Indexed
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 327 of 589
lhaux
Load Halfword Algebraic with Update Indexed
EA ← (RA|0) + (RB)
(RA)
← EA
(RT)
← EXTS(MS(EA,2))
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is
placed into register RA.
The halfword at the EA is sign-extended to 32 bits and placed into register RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•RA
•RT
Invalid Instruction Forms
• Reserved fields
• RA=RT
• RA=0
lhaux RT, RA, RB
31 RT RA RB 375
0 6 11 16 21 31