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User’s Manual
PPC440x5 CPU Core Preliminary
Page 584 of 583
ppc440x5IX.fm.
September 12, 2002
privileged mode, 80
privileged operation
, 80
privileged SPRs
, 81
problem state
, 80
processor control instruction summary
, 60
processor control instructions
CR logical
, 61
register management
, 61
synchronization
, 61
system linkage
, 61
processor control registers
, 74
Program interrupt
, 187
program interrupts
, 187
pseudocode
, 251
PVR
, 75, 508
R
R0-R31, 489
reading the time base
, 210
register
CSRR0
, 168, 169
CSRR1
, 168, 169
ESR
, 172
PID
, 151
SRR0
, 167
SRR1
, 167
registers
, 47
branching control
, 66
CCR0
, 76, 108, 110, 126, 460
CCR1
, 462
CR
, 52, 67, 464
CSRR0
, 465
CSRR1
, 466
CTR
, 67, 467
DAC1–DAC2
, 246, 468
DBCR0
, 239, 243, 469
DBCR1
, 240, 471
DBCR2
, 473
DBDR
, 247
DBSR
, 244
DCDBTRH
, 127, 478
DCDBTRL
, 127, 479
DCR numbering
, 457
DEAR
, 480
DEC
, 211, 481
DECAR
, 211, 482
DNV0–DNV3
, 483
DTV0–DTV3
, 484
DVC1–DVC2
, 246
DVLIM
, 486
ESR
, 172, 487
GPR0-GPR31
, 489
GPRs
, 71
IAC1-IAC4
, 485, 490
IAC1–IAC4
, 245
ICDBDR
, 491
ICDBTRH
, 492
ICDBTRL
, 493
interrupt processing
, 165
INV0–INV3
, 494
ITV0–ITV3
, 495
IVLIM
, 496
IVOR0–IVOR15
, 497
IVPR
, 498
LR
, 66, 499
MCSR
, 500
MCSRR0
, 501
MCSRR1
, 502
MMUCR
, 148, 503
MSR
, 53, 165, 504
PID
, 506
PIR
, 76, 507
processor control
, 74
PVR
, 75, 508
R0-R31
, 489
RSTCFG
, 79, 509
SPRG0 SPRG7
, 75
SPRG0-SPRG3
, 75
SPRG0-SPRG7
, 510
SRR0
, 511
SRR1
, 512
storage control
, 147
TBL
, 513
TBU
, 514
TCR
, 212, 213, 215, 515
TSR
, 214, 216, 516
types
, 52
CR
, 52
DCR
, 53
GPR
, 52
MSR
, 53
SPR
, 52
USPRG0
, 75, 517
XER
, 72, 518
registers, device control
, 53
registers, summary
, 47
replacement policy, cache line
, 96
requirements
software
interrupt ordering
, 199
reservation bit
, 339, 424
reserved instructions, exception priorities for
, 207
reserved-illegal instructions
, 558
reserved-nop instructions
, 558
reset
debug
, 238
return (RET) debug events
, 235
return from interrupt instructions, exception priorities for
,
207
rfci
, 396