Filter
Top Products
User’s Manual
PPC440x5 CPU Core Preliminary
Page 162 of 589
intrupts.fm.
September 12, 2002
properly be classified as either synchronous or asynchronous, nor as precise or imprecise. They also do not
belong to either the critical or the non-critical interrupt class, but instead have associated with them a unique
pair of save/restore registers, Machine Check Save/Restore Registers 0/1 (MCSRR0/1).
Architecturally, the following general rules apply for Machine Check interrupts:
1. No instruction after the one whose address is reported to the Machine Check interrupt handler in
MCSRR0 has begun execution.
2. The instruction whose address is reported to the Machine Check interrupt handler in MCSRR0, and all
prior instructions, may or may not have completed successfully. All those instructions that are ever going
to complete appear to have done so already, and have done so within the context existing prior to the
Machine Check interrupt. No further interrupt (other than possible additional Machine Check interrupts)
will occur as a result of those instructions.
With the PPC440x5, Machine Check interrupts can be caused by Machine Check exceptions on a memory
access for an instruction fetch, for a data access, or for a TLB access. Some of the interrupts generated
behave as synchronous, precise interrupts, while other are handled in an asynchronous fashion.
In the case of an Instruction Synchronous Machine Check exception, the PPC440x5 will handle the interrupt
as a synchronous, precise interrupt, assuming Machine Check interrupts are enabled (MSR[ME] = 1). That is,
if a Machine Check exception is detected during an instruction fetch, the exception will not be reported to the
interrupt mechanism unless and until execution is attempted for the instruction address at which the Machine
Check exception occurred. If, for example, the direction of the instruction stream is changed (perhaps due to
a branch instruction), such that the instruction at the address associated with the Machine Check exception
will not be executed, then the exception will not be reported and no interrupt will occur. If and when an
Instruction Machine Check exception is reported, and if Machine Check interrupts are enabled at the time of
the reporting of the exception, then the interrupt will be synchronous and precise and MCSRR0 will be set to
the instruction address which led to the exception. If Machine Check interrupts are not enabled at the time of
the reporting of an Instruction Machine Check exception, then a Machine Check interrupt will not be gener-
ated (ever, even if and when MSR[ME] is subsequently set to 1), although the ESR[MCI] field will be set to 1
to indicate that the exception has occurred and that the instruction associated with the exception has been
executed.
Instruction Asynchronous Machine Check, Data Asynchronous Machine Check, and TLB Asynchronous
Machine Check exceptions, on the other hand, are handled in an “asynchronous” fashion. That is,the address
reported in MCSRR0 may not be related to the instruction which prompted the access which led , directly or
indirectly, to the Machine Check exception. The address may be that of an instruction before or after the
exception-causing instruction, or it may reference the exception causing instruction, depending on the nature
of the access, the type of error encountered , and the circumstances of the instruction’s execution within the
processor pipeline. If MSR[ME] is 0 at the time of a Machine Check exception that is handled in this asyn-
chronous way, a Machine Check interrupt will subsequently occur if and when MSR[ME] is set to 1.
See Machine Check Interrupt on page 178 for more detailed information on Machine Check interrupts.
6.3 Interrupt Processing
Associated with each kind of interrupt is an interrupt vector, that is, the address of the initial instruction that is
executed when the corresponding interrupt occurs.