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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 187 of 589
Exception Syndrome Register (ESR)
FP Set to 1 if the instruction causing the interrupt is a floating-point load or store;
otherwise set to 0.
ST Set to 1 if the instruction causing the interrupt is a store, dcbz, or dcbi instruction;
otherwise set to 0.
AP Set to 1 if the instruction causing the interrupt is an auxiliary processor load or store;
otherwise set to 0.
All other defined ESR bits are set to 0.
6.5.7 Program Interrupt
A Program interrupt occurs when no higher priority exception exists, a Program exception is presented to the
interrupt mechanism, and -- for the Floating-Point Enabled form of Program exception only -- MSR[FE0,FE1]
is non-zero. The PPC440x5 core includes six types of Program exception. They are:
Illegal Instruction exception
An Illegal Instruction exception occurs when execution is attempted of any of the following
kinds of instructions:
• a reserved-illegal instruction
• when MSR[PR] = 1 (user mode), an mtspr or mfspr that specifies an SPRN value with SPRN
5
=0
(user-mode accessible) that represents an unimplemented Special Purpose Register. For mtspr, this
includes any SPR number other than the XER, LR, CTR, or USPRG0. For mfspr, this includes any
SPR number other than the ones listed for mtspr, plus SPRG4-7, TBH, and TBL.
• a defined instruction which is not implemented within the PPC440x5 core, and which is not a floating-
point instruction. This includes all instructions that are defined for 64-bit implementations only, as well
as tlbiva and mfapidi (see the PowerPC Book-E specification)
• a defined floating-point instruction that is not recognized by an attached floating-point unit (or when
no such floating-point unit is attached)
• an allocated instruction that is not implemented within the PPC440x5 core and which is not recog-
nized by an attached auxiliary processor (or when no such auxiliary processor is attached)
See Instruction Classes on page 53 for more information on the PPC440x5 core’s support for
defined and allocated instructions.
Privileged Instruction exception
A Privileged Instruction exception occurs when MSR[PR] = 1 and execution is attempted of
any of the following kinds of instructions:
• a privileged instruction
•anmtspr or mfspr instruction that specifies an SPRN value with SPRN
5
= 1 (a Privileged Instruction
exception occurs regardless of whether or not the SPR referenced by the SPRN value is defined)
Trap exception
A Trap exception occurs when any of the conditions specified in a tw or twi instruction are
met. However, if Trap debug events are enabled (DBCR0[TRAP]=1), internal debug mode is
enabled (DBCR0[IDM]=1), and Debug interrupts are enabled (MSR[DE]=1), then a Trap