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User’s Manual
PPC440x5 CPU Core Preliminary
Page 192 of 589
intrupts.fm.
September 12, 2002
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Programming Note: Software is responsible for clearing the Decrementer exception status
by writing to TSR[DIS], prior to reenabling MSR[EE], in order to avoid
another, redundant Decrementer interrupt.
6.5.12 Fixed-Interval Timer Interrupt
A Fixed-Interval Timer interrupt occurs when no higher priority exception exists, a Fixed-Interval Timer excep-
tion exists (TSR[FIS] = 1), and the interrupt is enabled (TCR[FIE] = 1 and MSR[EE]=1). See Chapter 7,
“Timer Facilities” for more information on Fixed Interval Timer exceptions.
Note: MSR[EE] also enables the External Input and Decrementer interrupts.
When a Fixed interval Timer interrupt occurs, the interrupt processing registers are updated as indicated
below (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] ||
IVOR11[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the next instruction to be executed.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Programming Note: Software is responsible for clearing the Fixed Interval Timer exception
status by writing to TSR[FIS], prior to reenabling MSR[EE], in order to
avoid another, redundant Fixed Interval Timer interrupt.
6.5.13 Watchdog Timer Interrupt
A Watchdog Timer interrupt occurs when no higher priority exception exists, a Watchdog Timer exception
exists (TSR[WIS] = 1), and the interrupt is enabled (TCR[WIE] = 1 and MSR[CE] = 1). See Chapter 7, “Timer
Facilities” for more information on Watchdog Timer exceptions.
Note: MSR[CE] also enables the Critical Input interrupt.
When a Watchdog Timer interrupt occurs, the interrupt processing registers are updated as indicated below
(all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] ||
IVOR12[IVO] || 0b0000.