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User’s Manual
PPC440x5 CPU Core Preliminary
Page 188 of 589
intrupts.fm.
September 12, 2002
exception will cause a Debug interrupt to occur, rather than a Program interrupt.
See Chapter 8, “Debug Facilities” for more information on Trap debug events.
Unimplemented Operation exception
An Unimplemented Operation exception occurs when execution is attempted of any of the
following kinds of instructions:
• a defined floating-point instruction that is recognized but not supported by an attached floating-point
unit, when floating-point instruction processing is enabled (MSR[FP]=1).
• an allocated instruction that is not implemented within the PPC440x5 core, and is recognized but not
supported by an attached auxiliary processor, when auxiliary processor instruction processing is
enabled. The enabling of auxiliary processor instruction processing is implementation-dependent.
Floating-Point Enabled exception
A Floating-Point Enabled exception occurs when the execution or attempted execution of a
defined floating-point instruction causes FPSCR[FEX] to be set to 1, in an attached floating-
point unit. FPSCR[FEX] is the Floating-Point Status and Control Register Floating-Point Ena-
bed Exception Summary bit (see the user’s manual for the floating-point unit implementation
for more details).
If MSR[FE0,FE1] is non-zero when the Floating-Point Enabled exception is presented to the
interrupt mechanism, then a Program interrupt will occur, and the interrupt processing regis-
ters will be updated as described below. If MSR[FE0,FE1] are both 0, however, then a
Program interrupt will not occur and the instruction associated with the exception will exe-
cute according to the definition of the floating-point unit (see the user’s manual for the
floating-point unit implementation). If and when MSR[FE0,FE1] are subsequently set to a
non-zero value, and the Floating-Point Enabled exception is still being presented to the inter-
rupt mechanism (that is, FPSCR[FEX] is still set), then a “delayed” Program interrupt will
occur, updating the interrupt processing registers as described below.
See Synchronous, Imprecise Interrupts on page 160 for more information on this special
form of “delayed” Floating-Point Enabled exception.
Auxiliary Processor Enabled exception
An Auxiliary Processor Enabled exception may occur due to the execution or attempted exe-
cution of an allocated instruction that is not implemented within the PPC440x5 core, but is
recognized and supported by an attached auxiliary processor. The cause of such an excep-
tion is implementation-dependent. See the user’s manual for the auxiliary processor
implementation for more details.
When a Program interrupt occurs, the processor suppresses the execution of the instruction causing the
Program exception (for all cases except the “delayed” form of Floating-Point Enabled exception described
above), the interrupt processing registers are updated as indicated below (all registers not listed are
unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR6[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the instruction causing the Program interrupt, for all cases
except the “delayed” form of Floating-Point Enabled exception described above.
For the special case of the delayed Floating-Point Enabled exception, where the exception