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addis
Add Immediate Shifted
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 261 of 589
addis
Add Immediate Shifted
(RT) ← (RA|0) + (IM ||
16
0)
If the RA field is 0, the IM field is concatenated on its right with sixteen 0-bits and placed into register RT.
If the RA field is nonzero, the contents of register RA are added to the contents of the extended IM field. The
sum is stored into register RT.
Registers Altered
•RT
Programming Note
An addi instruction stores a sign-extended 16-bit value in a GPR. An addis instruction followed by an ori
instruction stores an arbitrary 32-bit value in a GPR, as shown in the following example:
addis RT, 0, high 16 bits of value
ori RT, RT, low 16 bits of value
addis RT, RA, IM
15 RT RA IM
0 6 11 16 31
Table 9-7. Extended Mnemonics for addis
Mnemonic Operands Function
Other Registers
Altered
lis
RT, IM
Load immediate shifted.
(RT) ← (IM ||
16
0)
Extended mnemonic for
addis RT,0,IM
subis
RT, RA, IM
Subtract (IM ||
16
0) from (RA|0).
Place result in RT.
Extended mnemonic for
addis RT,RA,−IM