Filter
Top Products
User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 161 of 589
• No instruction following the instruction addressed by SRR0 or CSRR0 has executed.
The only synchronous, imprecise interrupts in the PPC440x5 core are the “special cases” of “delayed” inter-
rupts, which can result when certain kinds of exceptions occur while the corresponding interrupt type is
disabled. The first of these is the Floating-Point Enabled exception type Program interrupt. For this type of
interrupt to occur, a floating-point unit must be attached to the auxiliary processor interface of the PPC440x5
core, and the Floating-point Enabled Exception Summary bit of the Floating-Point Status and Control
Register (FPSCR[FEX]) must be set while Floating-point Enabled exception type Program interrupts are
disabled due to MSR[FE0,FE1] both being 0. If and when such interrupts are subsequently enabled, by
setting one or the other (or both) of MSR[FE0,FE1] to 1 while FPSCR[FEX] is still 1, then a synchronous,
imprecise form of Floating-Point Enabled exception type Program interrupt will occur, and SRR0 will be set to
the address of the instruction which would have executed next (that is, the instruction after the one which
updated MSR[FE0,FE1]). If the MSR was updated by an rfi, rfci, or rfmci instruction, then SRR0 will be set to
the address to which the rfi, rfci, or rfmci was returning, and not to the instruction address which is sequen-
tially after the rfi, rfci, or rfmci.
The second type of delayed interrupt which may be handled as a synchronous, imprecise interrupt is the
Debug interrupt. Similar to the Floating-Point Enabled exception type Program interrupt, the Debug interrupt
can be temporarily disabled by an MSR bit, MSR[DE]. Accordingly, certain kinds of Debug exceptions may
occur and be recorded in the DBSR while MSR[DE] is 0, and later lead to a delayed Debug interrupt if
MSR[DE] is set to 1 while a Debug exception is still set in the DBSR. If and when this occurs, the interrupt will
either be synchronous and imprecise, or it will be asynchronous, depending on the type of Debug exception
causing the interrupt. In either case, CSRR0 is set to the address of the instruction which would have
executed next (that is, the instruction after the one which set MSR[DE] to 1). If MSR[DE] is set to 1 by rfi, rfci,
or rfmci, then CSRR0 is set to the address to which the rfi, rfci, or rfmci was returning, and not to the
address of the instruction which was sequentially after the rfi, rfci, or rfmci.
Besides these special cases of Program and Debug interrupts, all other synchronous interrupts are handled
precisely by the PPC440x5 core, including FP Enabled exception type Program interrupts even when the
processor is operating in one of the architecturally-defined imprecise modes (MSR[FE0,FE1] = 0b01 or
0b10).
See Program Interrupt on page 187 and Debug Interrupt on page 195 for a more detailed description of these
interrupt types, including both the precise and imprecise cases.
6.2.3 Critical and Non-Critical Interrupts
Interrupts can also be classified as critical or noncritical interrupts. Certain interrupt types demand immediate
attention, even if other interrupt types are currently being processed and have not yet had the opportunity to
save the state of the machine (that is, return address and captured state of the MSR). To enable taking a crit-
ical interrupt immediately after a non-critical interrupt has occurred (that is, before the state of the machine
has been saved), two sets of Save/Restore Register pairs are provided. Critical interrupts use the
Save/Restore Register pair CSRR0/CSRR1. Non-Critical interrupts use Save/Restore Register pair
SRR0/SRR1.
6.2.4 Machine Check Interrupts
Machine Check interrupts are a special case. They are typically caused by some kind of hardware or storage
subsystem failure, or by an attempt to access an invalid address. A Machine Check may be caused indirectly
by the execution of an instruction, but not be recognized and/or reported until long after the processor has
executed past the instruction that caused the Machine Check. As such, Machine Check interrupts cannot