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User’s Manual
PPC440x5 CPU Core Preliminary
Page 62 of 589
prgmodel.fm.
September 12, 2002
Table 2-17 shows the processor synchronization instruction in the PPC440x5.
2.4.4 Storage Control Instructions
These instructions manage the instruction and data caches and the TLB of the PPC440x5 core. Instructions
are also provided to synchronize and order storage accesses. The instructions in these three sub-categories
of storage control instructions are described below.
2.4.4.1 Cache Management Instructions
These instructions control the operation of the data and instruction caches. Instructions are provided to fill,
flush, invalidate, or zero data cache blocks, where a block is defined as a 32-byte cache line. instructions are
also provided to fill or invalidate instruction cache blocks.
Table 2-18 lists the cache management instructions in the PPC440x5.
2.4.4.2 TLB Management Instructions
The TLB management instructions read and write entries of the TLB array, and search the TLB array for an
entry which will translate a given virtual address. There is also an instruction for synchronizing TLB updates
with other processors, but since the PPC440x5 core is intended for use in uni-processor environments, this
instruction performs no operation on the PPC440x5.
Table 2-19 lists the TLB management instructions in the PPC440x5. See Integer Arithmetic Instructions on
page 58 for an explanation of the “[.]” syntax.
Table 2-17. Processor Synchronization Instruction
isync
Table 2-18. Cache Management Instructions
Data Cache Instruction Cache
dcba
dcbf
dcbi
dcbst
dcbt
dcbtst
dcbz
icbi
icbt
Table 2-19. TLB Management Instructions
tlbre
tlbsx
[.]
tlbsync
tlbwe