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User’s Manual
PPC440x5 CPU Core Preliminary
Page 234 of 589
debug.fm.
September 12, 2002
lswx, stswx
DVC debug events do not occur for lswx or stswx instructions with a length of 0
(XER[TBC] = 0), since these instructions do not actually access storage.
8.3.4 Branch Taken (BRT) Debug Event
BRT debug events occur when BRT debug events are enabled (DBCR0[BRT] = 1) and execution is
attempted of a branch instruction for which the branch condition(s) are satisfied, such that the instruction
stream will be redirected to the target address of the branch.
When operating in external debug mode or debug wait mode, the occurrence of a BRT debug event is
recorded in DBSR[BRT] and causes the instruction execution to be suppressed. The processor then enters
the stop state and ceases the processing of instructions. The program counter will contain the address of the
branch instruction which caused the BRT debug event. Similarly, when operating in internal debug mode with
Debug interrupts enabled (MSR[DE] = 1), the occurrence of a BRT debug event is recorded in DBSR[BRT]
and causes the instruction execution to be suppressed. A Debug interrupt will occur with CSRR0 set to the
address of the branch instruction which caused the BRT debug event.
When operating in internal debug mode (and not also in external debug mode nor debug wait mode) with
Debug interrupts disabled (MSR[DE] = 0), then BRT debug events cannot occur. Since taken branches are a
very common operation and thus likely to be frequently executed within the critical class interrupt handlers
(which typically have MSR[DE] set to 0), allowing BRT debug events under these conditions would lead to an
undesirable number of delayed (and hence imprecise) Debug interrupts.
When operating in trace mode, the occurrence of a BRT debug event is simply recorded in DBSR[BRT] and is
indicated over the trace interface, and instruction execution continues.
8.3.5 Trap (TRAP) Debug Event
TRAP debug events occur when TRAP debug events are enabled (DBCR0[TRAP] = 1) and execution is
attempted of a trap (tw, twi) instruction for which the trap condition is satisfied.
When operating in external debug mode or debug wait mode, the occurrence of a TRAP debug event is
recorded in DBSR[TRAP] and causes the instruction execution to be suppressed. The processor then enters
the stop state and ceases the processing of instructions. The program counter will contain the address of the
trap instruction which caused the TRAP debug event. Similarly, when operating in internal debug mode with
Debug interrupts enabled (MSR[DE] = 1), the occurrence of a TRAP debug event is recorded in
DBSR[TRAP] and causes the instruction execution to be suppressed. A Debug interrupt will occur with
CSRR0 set to the address of the trap instruction which caused the TRAP debug event.
When operating in internal debug mode (and not also in external debug mode nor debug wait mode) with
Debug interrupts disabled (MSR[DE] = 0), the occurrence of a TRAP debug event will set DBSR[TRAP],
along with the Imprecise Debug Event (IDE) field of the DBSR. Although a Debug interrupt will not occur
immediately, the instruction execution is suppressed as a Trap exception type Program interrupt will occur
instead. A Debug interrupt will also occur later, if and when MSR[DE] is set to 1, thereby enabling Debug
interrupts, assuming software has not cleared the TRAP debug event status from the DBSR in the meantime.
Upon such a “delayed” interrupt, the Debug interrupt handler software may query the DBSR[IDE] field to
determine that the Debug interrupt has occurred imprecisely.
When operating in trace mode, the occurrence of a TRAP debug event is simply recorded in DBSR[TRAP]
and is indicated over the trace interface, and instruction execution continues.