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mtcrf
Move to Condition Register Fields
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 367 of 589
mtcrf
Move to Condition Register Fields
mask ←
4
(FXM
0
) ||
4
(FXM
1
) || ... ||
4
(FXM
6
) ||
4
(FXM
7
)
(CR)
← ((RS) ∧ mask) ∨ ((CR) ∧¬mask)
Some or all of the contents of register RS are placed into the CR as specified by the FXM field.
Each bit in the FXM field controls the copying of 4 bits in register RS into the corresponding bits in the CR.
The correspondence between the bits in the FXM field and the bit copying operation is shown in the following
table:
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•CR
Invalid Instruction Forms
• Reserved fields
mtcrf FXM, RS
31 RS FXM 144
0 6 11 12 20 21 31
Table 9-20. FXM Bit Field Correspondence
FXM Bit Number CR Bits Affected
0 0:3
1 4:7
2 8:11
3 12:15
4 16:19
5 20:23
6 24:27
7 28:31
Table 9-21. Extended Mnemonics for mtcrf
Mnemonic Operands Function
mtcr
RS
Move to CR.
Extended mnemonic for
mtcrf 0xFF,RS