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User’s Manual
Preliminary PPC440x5 CPU Core
mmu.fm.
September 12, 2002
Page 151 of 589
Search Translation ID (STID) Field
The STID field is used by the tlbsx[.] instruction to designate the process identifier value to be compared with
the TID field of the TLB entries. For instruction fetch and data storage accesses and cache management
operations, the TID field of the TLB entries is compared with the value in the PID register (see Process ID
(PID) on page 151). For tlbsx[.] however, the MMUCR[STID] field is used, allowing the TLB to be searched
for entries with a TID field which does not match the Process ID of the currently executing process.
The MMUCR[STID] field is also used to transfer the TLB entry’s TID field on tlbre and tlbwe instructions
which target TLB word 0, as there are not enough bits in the GPR used for transferring the other fields such
that it could hold this field as well.
See TLB Match Process on page 139 for more information on the TLB entry TID field and the address
matching process. Also see TLB Read/Write Instructions (tlbre/tlbwe) on page 153 for more information on
how the MMUCR[STID] field is used by these instructions.
5.7.2 Process ID (PID)
The Process ID (PID) is a 32-bit register, although only the lower 8 bits are defined in the PPC440x5 core.
The 8-bit PID value is used as a portion of the virtual address for accessing storage (see Virtual Address
Formation on page 138). The PID value is compared against the TID field of a TLB entry to determine
whether or not the entry corresponds to a given virtual address. If an entry’s TID field is 0 (signifying that the
entry defines a “global” as opposed to “private” page), then the PID value is ignored when determining
whether the entry corresponds to a given virtual address. See TLB Match Process on page 139 for a more
detailed description of the use of the PID value in the TLB match process.
The PID is written from a GPR using mtspr, and can be read into a GPR using mfspr. The following figure
illustrates the PID.
5.8 Shadow TLB Arrays
The PPC440x5 core implements two shadow TLB arrays, one for instruction fetches and one for data
accesses. These arrays “shadow” the value of a subset of the entries in the main, unified TLB (the UTLB in
the context of this discussion). The purpose of the shadow TLB arrays is to reduce the latency of the address
translation operation, and to avoid contention for the UTLB array between instruction fetches and data
accesses.
Figure 5-4. Process ID (PID)
0:23 Reserved
24:31 Process ID
0 23 24 31