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User’s Manual
PPC440x5 CPU Core Preliminary
Page 574 of 583
ppc440x5IX.fm.
September 12, 2002
data addressing modes, 41
data cache
coherency
, 124
data cache array organization and operation
, 95
data cache controller. See DCC
data cache line allocation on store miss
, 119
data read PLB interface requests
PLB interface
, 122
data read requests
, 122
data storage addressing modes
, 41
Data Storage interrupt
, 181
data storage interrupts
, 181
Data TLB Error interrupt
, 193
data TLB error interrupts
, 193
data value compare See also DVC
, 231
data write PLB interface requests
PLB interface
, 123
data write requests
, 123
DBCR0
, 239, 243, 469
DBCR1
, 240, 471
DBCR2
, 473
DBDR
, 247
DBSR
, 244
dcba
operation summary
, 125
dcbf
, 296
operation summary
, 125
dcbi
, 297
operation summary
, 125
dcbst
, 298
operation summary
, 125
dcbt
formal description
, 299
functional description
, 126
operation summary
, 125
dcbt and dcbtst operation
, 126
dcbtst
formal description
, 300
functional description
, 126
operation summary
, 125
dcbz
, 302
operation summary
, 125
DCC (data cache controller)
control
, 125
debug
, 125
features
, 115
operations
, 116
dccci
, 304
operation summary
, 125
DCDBTRH
, 127, 478
DCDBTRL
, 127, 479
dcread
functional description
, 127, 305
operation summary
, 125
DCRs
defined
, 53
DEAR
, 480
debug
debug cache
, 125
instruction cache
, 108
debug events
BRT
, 234
DAC
, 226
DAC fields
, 226
DVC
, 231
DVC fields
, 232
IAC
, 222, 235
IAC fields
, 222
ICMP
, 235
IPRT
, 236
overview
, 221
RET
, 235
summary
, 237
TRAP
, 234
UDE
, 237
Debug Interrupt
, 195
debug interrupts
, 195
debug modes
debug wait
, 220
external
, 220
internal
, 219
overview
, 219
trace
, 221
debug wait mode
, 220
debugging
debug events
, 221
debug modes
, 219
development tool support
, 219
registers
DAC1–DAC2
, 246
DBCR0
, 239, 243
DBCR1
, 240
DBDR
, 247
DBSR
, 244
DVC1–DVC2
, 246
IAC1–IAC4
, 245
overview
, 238
reset
, 238
timer freeze
, 238
DEC
, 211, 481
DECAR
, 211, 482
Decrementer Interrupt
, 191
decrementer interrupts
, 191
device control registers
, 53
Device Control Registers. See also DCRs
direct write to memory
, 119
divw
, 307
divw.
, 307
divwo
, 307
divwo.
, 307
divwu
, 308
divwu.
, 308