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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 189 of 589
was already being presented to the interrupt mechanism at the time MSR[FE0,FE1] was
changed from 0 to a non-zero value, SRR0 is set to the address of the instruction that would
have executed after the MSR-changing instruction. If the instruction which set
MSR[FE0,FE1] was
rfi, rfci, or rfmci, then CSRR0 is set to the address to which the rfi, rfci,
or rfmci was returning, and not to the address of the instruction which was sequentially after
the
rfi, rfci, or rfmci.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Exception Syndrome Register (ESR)
PIL Set to 1 for an Illegal Instruction exception; otherwise set to 0
PPR Set to 1 for a Privileged Instruction exception; otherwise set to 0
PTR Set to 1 for a Trap exception; otherwise set to 0
PUO Set to 1 for an Unimplemented Operation exception; otherwise set to 0
FP Set to 1 if the instruction causing the interrupt is a floating-point instruction;
otherwise set to 0.
AP Set to 1 if the instruction causing the interrupt is an auxiliary processor instruction;
otherwise set to 0.
PIE Set to 1 if a “delayed” form of Floating-point Enabled exception type Program
interrupt; otherwise set to 0. The setting of ESR[PIE] to 1 indicates to the Program
interrupt handler that the interrupt was imprecise due to being caused by the
changing of MSR[FE0,FE1] and not directly by the execution of the floating-point
instruction which caused the exception by setting FPSCR[FEX]. Thus the Program
interrupt handler can recognize that SRR0 contains the address of the instruction
after the MSR-changing instruction, and not the address of the instruction that
caused the Floating-Point Enabled exception.
PCRE Set to 1 if a Floating-Point Enabled exception and the floating-point instruction which
caused the exception was a CR-updating instruction. Note that ESR[PCRE] is
undefined if ESR[PIE] is 1.
PCMP Set to 1 if a Floating-Point Enabled exception and the instruction which caused the
exception was a floating-point compare instruction. Note that ESR[PCMP] is
undefined if ESR[PIE] is 1.
PCRF Set to the number of the CR field (0 - 7) which was to be updated, if a Floating-Point
Enabled exception and the floating-point instruction which caused the exception was
a CR-updating instruction. Note that ESR[PCRF] is undefined if ESR[PIE] is 1.
All other defined ESR bits are set to 0.