Filter
Top Products
User’s Manual
PPC440x5 CPU Core Preliminary
Page 240 of 589
debug.fm.
September 12, 2002
8.6.2 Debug Control Register 1 (DBCR1)
DBCR1 is an SPR that is used to configure IAC debug events. DBCR1 can be written from a GPR using
mtspr, and can be read into a GPR using mfspr.
9 IAC2
IAC 2 Debug Event
0 Disable IAC 2 debug event.
1 Enable IAC 2 debug event.
10 IAC3
IAC 3 Debug Event
0 Disable IAC 3 debug event.
1 Enable IAC 3 debug event.
11 IAC4
IAC 4 Debug Event
0 Disable IAC 4 debug event.
1 Enable IAC 4 debug event.
12 DAC1R
Data Address Compare (DAC) 1 Read Debug Event
0 Disable DAC 1 read debug event.
1 Enable DAC 1 read debug event.
13 DAC1W
DAC 1 Write Debug Event
0 Disable DAC 1 write debug event.
1 Enable DAC 1 write debug event.
14 DAC2R
DAC 2 Read Debug Event
0 Disable DAC 2 read debug event.
1 Enable DAC 2 read debug event.
15 DAC2W
DAC 2 Write Debug Event
0 Disable DAC 2 write debug event.
1 Enable DAC 2 write debug event.
16 RET
Return Debug Event
0 Disable return (rfi/rfci/rfmci) debug event.
1 Enable return (rfi/rfci/rfmci) debug event.
rfci/rfmci does not cause a return
debug event if MSR[DE] = 0 in internal
debug mode, unless also in external
debug mode or debug wait mode.
17:30 Reserved
31 FT
Freeze timers on debug event
0 Timers are not frozen.
1 Freeze timers if a DBSR field associated with a debug event
is set.
Figure 8-2. Debug Control Register 1 (DBCR1)
0:1 IAC1US
Instruction Address Compare (IAC) 1 User/Super-
visor
00 Both
01 Reserved
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
012345678910 14 15 16 17 18 19 20 21 22 23 24 25 26 30 31
IAC1US
IAC1ER
IAC2US
IAC12M
IAC12AT
IAC3US
IAC3ER
IAC4US
IAC34M
IAC4ER
IAC34A
T
IAC2ER