IBM PPC440X5 Computer Hardware User Manual


 
User’s Manual
PPC440x5 CPU Core Preliminary
Page 454 of 589
regsummIntro.fm.
September 12, 2002
Table 10-2 Special Purpose Registers Sorted by SPR Number on page 454, lists the Special Purpose Regis-
ters (SPRs) in order by SPR number (SPRN). The table provides mnemonics, names, SPRN, model (user or
supervisor), and access. All SPR numbers not listed are reserved, and should be neither read nor written.
Note that three registers, DBSR, MCSR, and TSR, are indicated as having the access type of read/clear.
These three registers are status registers, and as such behave differently than other SPRs when written. The
term “read/clear” does not mean that these registers are automatically cleared upon being read. Rather, the
“clear” refers to their behavior when being written. Instead of simply overwriting the SPR with the data in the
source GPR, the status SPR is updated by zeroing those bit positions corresponding to 1 values in the source
GPR, with those bit positions corresponding to 0 values in the source GPR being left unchanged. In this
fashion, it is possible for software to read one of these status SPRs, and then write to it using the same data
which was read. Any bits which were read as 1 will then be cleared, and any bits which were not yet set at the
time the SPR was read will be left unchanged. If any of these previously clear bits happen to be set between
the time the SPR is read and when it is written, then when the SPR is later read again, software will observe
any newly set bit[s]. If it were not for this behavior, then software could erroneously clear bits which it had not
yet observed as having been set, and overlook the occurrence of certain exceptions.
Table 10-2. Special Purpose Registers Sorted by SPR Number
Mnemonic Register Name SPRN Model Access
XER Integer Exception Register 0x001 User Read/Write
LR Link Register 0x008 User Read/Write
CTR Count Register 0x009 User Read/Write
DEC Decrementer 0x016 Supervisor Read/Write
SRR0 Save/Restore Register 0 0x01A Supervisor Read/Write
SRR1 Save/Restore Register 1 0x01B Supervisor Read/Write
PID Process ID 0x030 Supervisor Read/Write
DECAR Decrementer Auto-Reload 0x036 Supervisor Write-only
CSRR0 Critical Save/Restore Register 0 0x03A Supervisor Read/Write
CSRR1 Critical Save/Restore Register 1 0x03B Supervisor Read/Write
DEAR Data Exception Address Register 0x03D Supervisor Read/Write
ESR Exception Syndrome Register 0x03E Supervisor Read/Write
IVPR Interrupt Vector Prefix Register 0x03F Supervisor Read/Write
USPRG0 User Special Purpose Register General 0 0x100 User Read/Write
SPRG4 Special Purpose Register General 4 0x104 User Read-only
SPRG5 Special Purpose Register General 5 0x105 User Read-only
SPRG6 Special Purpose Register General 6 0x106 User Read-only
SPRG7 Special Purpose Register General 7 0x107 User Read-only
TBL Time Base Lower 0x10C User Read-only
TBU Time Base Upper 0x10D User Read-only
SPRG0 Special Purpose Register General 0 0x110 Supervisor Read/Write
SPRG1 Special Purpose Register General 1 0x111 Supervisor Read/Write
SPRG2 Special Purpose Register General 2 0x112 Supervisor Read/Write