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dcread
Data Cache Read
PPC440x5 CPU Core User’s Manual Preliminary
Page 306 of 589
instrset.fm.
September 12, 2002
Registers Altered
•RT
• DCDBTRH
• DCDBTRL
Invalid Instruction Forms
• Reserved fields
Programming Note
Execution of this instruction is privileged.
The PPC440x5 core does not support the use of the dcread instruction when the data cache controller is still
in the process of performing cache operations associated with previously executed instructions (such as line
fills and line flushes). Also, the PPC440x5 core does not automatically synchronize context between a
dcread instruction and the subsequent mfspr instructions that read the results of the dcread instruction into
GPRs. In order to guarantee that the dcread instruction operates correctly, and that the mfspr instructions
obtain the results of the dcread instruction, a sequence such as the following must be used:
msync # ensure that all previous cache operations have completed
dcread regT,regA,regB# read cache information; the contents of GPR A and GPR B are
# added and the result used to specify a cache line index to be read;
# the data word is moved into GPR T and the tag information is read
# into DCDBTRH and DCDBTRL
isync # ensure dcread completes before attempting to read results
mfdcdbtrh regD # move high portion of tag into GPR D
mfdcdbtrl regE # move low portion of tag into GPR E
Architecture Note
This instruction is implementation-specific and programs which use this instruction may not be portable to
other PowerPC Book-E implementations. See Instruction Set Portability on page 250.