IBM PPC440X5 Computer Hardware User Manual


 
User’s Manual
PPC440x5 CPU Core Preliminary
Page 60 of 589
prgmodel.fm.
September 12, 2002
2.4.1.7 Integer Shift Instructions
Table 2-11 lists the integer shift instructions in the PPC440x5. Note that the shift right algebraic insructions
implicitly update the XER[CA] field. See Integer Arithmetic Instructions on page 58 for an explanation of the
“[
.]” syntax.
2.4.1.8 Integer Select Instruction
Table 2-12 lists the integer select instruction in the PPC440x5. The RA operand is 0 if the RA field of the
instruction is 0, or is the contents of GPR[RA] otherwise.
2.4.2 Branch Instructions
These instructions unconditionally or conditionally branch to an address. Conditional branch instructions can
test condition codes set in the CR by a previous instruction and branch accordingly. Conditional branch
instructions can also decrement and test the Count Register (CTR) as part of branch determination, and can
save the return address in the Link Register (LR).The target address for a branch can be a displacement from
the current instruction address or an absolute address, or contained in the LR or CTR.
See Branch Processing on page 64 for more information on branch operations.
Table 2-13 lists the branch instructions in the PPC440x5. In the table, the syntax “[
l]” indicates that the
instruction has both a “link update” form (which updates LR with the address of the instruction after the
branch) and a “non-link update” form. Similarly, the syntax “[a]” indicates that the instruction has both an
“absolute address” form (in which the target address is formed directly using the immediate field specified as
part of the instruction) and a “relative” form (in which the target address is formed by adding the specified
immediate field to the address of the branch instruction).
2.4.3 Processor Control Instructions
Processor control instructions manipulate system registers, perform system software linkage, and synchro-
nize processor operations. The instructions in these three sub-categories of processor control instructions are
described below.
Table 2-11. Integer Shift Instructions
Shift Left Shift Right
Shift Right
Algebraic
slw[.] srw[.]
sraw[.]
srawi[.]
Table 2-12. Integer Select Instruction
Integer Select
isel
Table 2-13. Branch Instructions
Branch
b[l][a]
bc[l][a]
bcctr[l]
bclr[l]