Filter
Top Products
tw
Trap Word
PPC440x5 CPU Core User’s Manual Preliminary
Page 440 of 589
instrset.fm.
September 12, 2002
tw
Trap Word
if ( ((RA) (RB) ∧ TO
0
=1) ∨
((RA) (RB) ∧ TO
1
=1) ∨
((RA) (RB) ∧ TO
2
=1) ∨
((RA) (RB) ∧ TO
3
=1) ∨
((RA) (RB) ∧ TO
4
=1) )
SRR0 ← address of tw instruction
SRR1 ← MSR
ESR[PTR] ← 1 (other bits cleared)
MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS]) ←
9
0
PC
← IVPR
0:15
|| IVOR6
16:27
||
4
0
else no operation
Register RA is compared with register RB. If any comparison condition enabled by the TO field is true, a Trap
exception type Program interrupt occurs as follows (see Program Interrupt on page 187 for more information
on Program interrupts). The contents of the MSR are copied into SRR1 and the address of the tw instruction)
is placed into SRR0. ESR[PTR] is set to 1 and the other bits ESR bits cleared to indicate the type of exception
causing the Program interrupt.
The program counter (PC) is then loaded with the interrupt vector address. The interrupt vector address is
formed by concatenating the high halfword of the Interrupt Vector Prefix Register (IVPR), bits 16:27 of the
Interrupt Vector Offset Register 6 (IVOR6), and 0b0000.
MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS] are set to 0.
Program execution continues at the new address in the PC.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• SRR0 (if trap condition is met)
• SRR1 (if trap condition is met)
• MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS] (if trap condition is met)
• ESR (if trap condition is met)
Invalid Instruction Forms
• Reserved fields
Programming Notes
This instruction can be inserted into the execution stream by a debugger to implement breakpoints, and is not
typically used by application code.
tw TO, RA, RB
31 TO RA RB 4
0 6 11 16 21 31
<
>
=
<
u
>
u