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User’s Manual
Preliminary PPC440x5 CPU Core
debug.fm.
September 12, 2002
Page 223 of 589
Note that the IAC range auto-toggle mechanism can “switch” the IAC range mode from inclusive to
exclusive, and vice-versa. See IAC Range Mode Auto-Toggle Field on page 224.
• Range exclusive comparison mode (DBCR1[IAC12M/IAC34M] = 0b11)
In this mode, the IAC1 or IAC2 event occurs only if the instruction address is outside the range
defined by the IAC1 and IAC2 register values, as follows: address < IAC1 or address ≥ IAC2. Simi-
larly, the IAC3 or IAC4 event occurs only if the instruction address is outside the range defined by the
IAC3 and IAC4 register values, as follows: address < IAC3 or address ≥ IAC4.
For a given IAC1/IAC2 or IAC3/IAC4 pair, when the instruction address falls outside the specified
range, either one or both of the corresponding IAC debug event bits will be set in the DBSR, as deter-
mined by which of the two corresponding IAC event enable bits are set in DBCR0. For example,
when the IAC1/IAC2 pair are set to range exclusive comparison mode, and the instruction address
falls outside the defined range, then DBCR1[IAC1, IAC2] will determine whether one or the other or
both of DBSR[IAC1, IAC2] are set. It is a programming error to set either of the IAC pairs to a range
comparison mode (either inclusive or exclusive) without also enabling at least one of the correspond-
ing IAC event enable bits in DBCR0.
Note that the IAC range auto-toggle mechanism can “switch” the IAC range mode from inclusive to
exclusive, and vice-versa. See IAC Range Mode Auto-Toggle Field on page 224.
The PowerPC Book-E architecture defines DBCR1[IAC12M/IAC34M] = 0b01 as IAC address bit
mask mode, but that mode is not supported by the PPC440x5, and that value of the
IAC12M/IAC34M fields is reserved.
IAC User/Supervisor Field
DBCR1[IAC1US, IAC2US, IAC3US, IAC4US] are the individual IAC user/supervisor fields for
each of the four IAC events. The IAC user/supervisor fields specify what operating mode the
processor must be in order for the corresponding IAC event to occur. The operating mode is
determined by the Problem State field of the Machine State Register (MSR[PR]; see User and
Supervisor Modes on page 80). When the IAC user/supervisor field is 0b00, the operating mode
does not matter; the IAC debug event may occur independent of the state of MSR[PR]. When this
field is 0b10, the processor must be operating in supervisor mode (MSR[PR] = 0). When this field
is 0b11, the processor must be operating in user mode (MSR[PR] = 1). The IAC user/supervisor
field value of 0b01 is reserved.
If a pair of IAC events (IAC1/IAC2 or IAC3/IAC4) are operating in range inclusive or range
exclusive mode, it is a programming error (and the results of any instruction address comparison
are undefined) if the corresponding pair of IAC user/supervisor fields are not set to the same
value. For example, if IAC1/IAC2 are operating in one of the range modes, then both
DBCR1[IAC1US] and DBCR1[IAC2US] must be set to the same value.
IAC Effective/Real Address Field
DBCR1[IAC1ER, IAC2ER, IAC3ER, IAC4ER] are the individual IAC effective/real address fields
for each of the four IAC events. The IAC effective/real address fields specify whether the
instruction address comparison should be performed using the effective, virtual, or real address
(see Memory Management on page 133) for an explanation of these different types of
addresses). When the IAC effective/real address field is 0b00, the comparison is performed using
the effective address only—the IAC debug event may occur independent of the instruction
address space (MSR[IS]). When this field is 0b10, the IAC debug event occurs only if the
effective address matches the IAC conditions and is in virtual address space 0 (MSR[IS] = 0).
Similarly, when this field is 0b11, the IAC debug event occurs only if the effective address