Filter
Top Products
User’s Manual
PPC440x5 CPU Core Preliminary
Page 90 of 589
init.fm.
September 12, 2002
2. Invalidate the instruction cache (iccci)
3. Invalidate the data cache (dccci)
4. Synchronize memory accesses (msync)
This step forces any data PLB operations that may have been in progress prior to the reset operation to
complete, thereby allowing subsequent data accesses to be initiated and completed properly.
5. Clear DBCR0 register (disable all debug events)
Although the PPC440x5 core is defined to reset some of the debug event enables during the reset oper-
ation (as specified in Table 3-1 on page 86), this is not required by the architecture and hence the initial-
ization software should not assume this behavior. Software should disable all debug events in order to
prevent non-deterministic behavior on the trace interface to the core.
6. Clear DBSR register (initialize all debug event status)
Although the PPC440x5 core is defined to reset the DBSR debug event status bits during the reset oper-
ation (as specified in Table 3-1 on page 86), this is not required by the architecture and hence the initial-
ization software should not assume this behavior. Software should clear all such status in order to
prevent non-deterministic behavior on the JTAG interface to the core.
7. Initialize CCR0 register
1. Enable/disable broadcast of instructions to auxiliary processor (save power if no AP attached)
2. Enable/disable broadcast of trace information (save power if not tracing)
3. Enable/configure or disable speculative instruction cache line prefetching
4. Specify behavior for icbt and dcbt/dcbtst instructions
5. Enable/disable gathering of separate store accesses
6. Enable/disable hardware support for misaligned data accesses
7. Enable/disable parity error recoverability (recoverability lowers load/store performance marginally.)
8. Enable/disable cache read of parity bits depending on s/w compatibility requirements
8. Initialize CCR1 register
1. enable/disable full-line flushes as desired.
2. disable force cache-op miss (FCOM) and various parity error insertion (xxxPEI).
3. Users may wish to initialize CCR1[TCS] here, or in the timer facilities section.
9. Configure instruction and data cache regions
These steps must be performed prior to enabling the caches by setting the caching inhibited storage
attribute of the corresponding TLB entry to 0.
1. Clear the instruction and data cache normal victim index registers (INV0–INV3, DNV0–DNV3)
2. Clear the instruction and data cache transient victim index registers (ITV0–ITV3, DTV0–DTV3)
3. Set the instruction and data cache victim limit registers (IVLIM and DVLIM) according to the desired
size of the normal, locked, and transient regions of each cache
10. Setup TLB entry to cover initial program memory page
Since the PPC440x5 core only initializes an architecturally-invisible shadow TLB entry during the reset
operation, and since all shadow TLB entries are invalidated upon any context synchronization, special