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User’s Manual
PPC440x5 CPU Core Preliminary
Page 194 of 589
intrupts.fm.
September 12, 2002
Save/Restore Register 0 (SRR0)
Set to the effective address of the instruction causing the Data TLB Error interrupt.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Data Exception Address Register (DEAR)
If the instruction causing the Data TLB Miss exception does so with respect to the memory
page targeted by the initial effective address calculated by the instruction, then the DEAR is
set to this calculated effective address. On the other hand, if the Data TLB Miss exception
only occurs due to the instruction causing the exception crossing a memory page boundary,
in that the missing TLB entry is for the page accessed after crossing the boundary, then the
DEAR is set to the address of the first byte within that page.
As an example, consider a misaligned load word instruction that targets effective address
0x00000FFF, and that the page containing that address is a 4KB page. The load word will
thus cross the page boundary, and attempt to access the next page starting at address
0x00001000. If a valid TLB entry does not exist for the first page, then the DEAR will be set
to 0x00000FFF. On the other hand, if a valid TLB entry does exist for the first page, but not
for the second, then the DEAR will be set to 0x00001000. Furthermore, the load word
instruction in this latter scenario will have been partially executed (see Partially Executed
Instructions on page 164).
Exception Syndrome Register (ESR)
FP Set to 1 if the instruction causing the interrupt is a floating-point load or store;
otherwise set to 0.
ST Set to 1 if the instruction causing the interrupt is a store, dcbz, or dcbi instruction;
otherwise set to 0.
AP Set to 1 if the instruction causing the interrupt is an auxiliary processor load or store;
otherwise set to 0.
MCI Unchanged.
All other defined ESR bits are set to 0.
6.5.15 Instruction TLB Error Interrupt
An Instruction TLB Error interrupt occurs when no higher priority exception exists and an Instruction TLB Miss
exception is presented to the interrupt mechanism. Note that although an Instruction TLB Miss exception may
occur during an attempt to fetch an instruction, such an exception is not actually presented to the interrupt
mechanism until an attempt is made to execute that instruction. An Instruction TLB Miss exception occurs
when an instruction fetch attempts to access a virtual address for which a valid TLB entry does not exist. See
Chapter 5, “Memory Management” for more information on the TLB.