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User’s Manual
PPC440x5 CPU Core Preliminary
Page 452 of 589
regsummIntro.fm.
September 12, 2002
Table 10-1. Register Categories
Register Category Register(s) Model and Access Type Page
Branch Control
CR User CR 67
CTR User SPR 67
LR User SPR 66
Cache Control
DNV0–DNV3 Supervisor SPR 97
DTV0–DTV3 Supervisor SPR 97
DVLIM Supervisor SPR 99
INV0–INV3 Supervisor SPR 97
ITV0–ITV3 Supervisor SPR 97
IVLIM Supervisor SPR 99
Cache Debug
DCDBTRH, DCDBTRL Supervisor, read-only SPR 127
ICDBDR, ICDBTRH, ICDBTRL
Supervisor, read-only SPR 112
Debug
DAC1–DAC2 Supervisor SPR 246
DBCR0–DBCR2 Supervisor SPR 239
DBDR Supervisor SPR 247
DBSR Supervisor SPR 244
DVC1–DVC2 Supervisor SPR 246
IAC1–IAC4 Supervisor SPR 245
Device Control
Implemented outside core Supervisor DCR 53
Integer Processing
GPR0–GPR31 User GPR 71
XER User SPR 72
Interrupt Processing
CSRR0–CSRR1 Supervisor SPR 168
DEAR Supervisor SPR 170
ESR Supervisor SPR 172
IVOR0–IVOR15 Supervisor SPR 170
IVPR Supervisor SPR 171
MCSR Supervisor SPR 174
MCSRR0-MCSRR1 Supervisor SPR 169
SRR0–SRR1 Supervisor SPR 167
Processor Control
CCR0 Supervisor SPR 108
CCR1 Supervisor SPR 108
MSR Supervisor MSR 165
PIR, PVR Supervisor, read-only SPR 75
RSTCFG Supervisor, read-only SPR 79
SPRG0–SPRG3 Supervisor SPR 75
SPRG4–SPRG7 User, read-only; Supervisor SPR 75
USPRG0 User SPR 75
Storage Control
MMUCR Supervisor SPR 148
PID Supervisor SPR 151