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User’s Manual
Preliminary PPC440x5 CPU Core
debug.fm.
September 12, 2002
Page 233 of 589
In this mode, at least one data byte lane that is enabled by a DVC byte enable field must be being
accessed and must match the corresponding byte data value in the corresponding DVC1 or DVC2
register.
• AND-OR comparison mode (DBCR2[DVC1M, DVC2M] = 0b11)
In this mode, the four byte lanes of an aligned word are divided into two pairs, with byte lanes 0 and 1
being in one pair, and byte lanes 2 and 3 in the other pair. The DVC comparison mode for each pair
of byte lanes operates in AND mode, and then the results of these two AND mode comparisons are
ORed together to determine whether a DVC debug event occurs. In other words, a DVC debug event
occurs if either one or both of the pairs of byte lanes satisfy the AND mode comparison requirements.
This mode may be used to cause a DVC debug event upon an access of a particular halfword data
value in either of the two halfwords of a word in memory.
8.3.3.2 DVC Debug Event Processing
The behavior of the PPC440x5 upon a DVC debug event depends on the setting of DBCR2[DAC12A]. This
field of DBCR2 controls whether DVC debug events are processed in a synchronous (DBCR2[DAC12A] = 0)
or an asynchronous (DBCR2[DAC12A] = 1) fashion. The processing of DVC debug events is the same as it is
for DAC debug events. See DAC Debug Event Processing on page 229 for more information.
8.3.3.3 DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses
Certain misaligned load and store instructions are handled by making multiple, independent storage
accesses. Similarly, load and store multiple and string instructions which access more than one register result
in more than one storage access. Load and Store Alignment on page 117 provides a detailed description of
the circumstances that lead to such multiple storage accesses being made as the result of the execution of a
single instruction.
Whenever the execution of a given instruction results in multiple storage accesses, the address and data of
each access is independently considered for whether or not it will cause a DVC debug event.
8.3.3.4 DVC Debug Events Applied to Various Instruction Types
Various special cases apply to the cache management instructions, the store word conditional indexed
(stwcx.) instruction, and the load and store string indexed (lswx, stswx) instructions, with regards to DVC
debug events. These special cases are as follows:
dcbz
The dcbz instruction is the only cache management instruction which can cause a DVC debug
event. dcbz is the only such instruction which actually writes new data to a storage location (in
this case, an entire 32-byte data cache line is written to zeroes).
stwcx.
If the execution of a stwcx. instruction would otherwise have caused a DVC write debug event,
but the processor does not have the reservation from a lwarx instruction, then the DVC write
debug event does not occur since the storage location does not get written.