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User’s Manual
PPC440x5 CPU Core Preliminary
Page 118 of 589
cache.fm.
September 12, 2002
The load and store string and multiple instructions are performed using one memory access for each four
bytes, unless and until an access would cross an aligned quadword boundary. The access that would cross
the boundary is shortened to access just the number of bytes left within the current quadword block, and then
the accesses are resumed with four bytes per access, starting at the beginning of the next quadword block,
until the end of the load or store string or multiple is reached.
The DCC handles all misaligned integer load and store accesses in hardware, without causing an Alignment
exception. However, the control bit CCR0[FLSTA] can be set to force all misaligned storage access instruc-
tions to cause an Alignment exception (see Figure 4-5 on page 109). When this bit is set, all integer storage
accesses must be aligned on an operand-size boundary, or an Alignment exception will result. Load and
store multiple instructions must be aligned on a 4-byte boundary, while load and store string instructions can
be aligned on any boundary (these instructions are considered to reference byte strings, and hence the
operand size is a byte).
The DCC also supports load and store operations over the AP interface. These can include floating-point load
and store instructions (as defined by PowerPC Book-E), as well as AP load and store instructions for auxiliary
processors. While floating-point loads and stores can access either four or eight bytes, AP loads and store
can access up to a sixteen bytes.
The DCC handles all misaligned floating-point and AP loads and stores with a single memory access, as long
as they do not cross a quadword boundary. If such an access crosses a quadword boundary, the DCC will
signal an Alignment exception and an interrupt will result.
The AP interface also supports other options with regards to the handling of misaligned AP and floating-point
loads and stores. The AP interface can specify that the DCC should signal an Alignment exception on any AP
or floating-point load or store access which is not aligned on either an operand-size boundary or a word
boundary. Alternatively, the AP interface can specify that the DCC should force the storage access to be
aligned on an operand-size boundary by zeroing the appropriate number of low-order address bits.
Floating-point and AP loads and stores are also subject to the function of CCR0[FLSTA].
4.3.1.2 Load Operations
Load instructions that reference cacheable memory pages and miss in the data cache result in cache line
read requests being presented to the data read PLB interface. Load operations to caching inhibited memory
pages, however, will only access the bytes specifically requested, according to the type of load instruction.
This behavior (of only accessing the requested bytes) is only architecturally required when the guarded
storage attribute is also set, but the DCC will enforce this requirement on any load to a caching inhibited
memory page. Subsequent load operations to the same caching inhibited locations will cause new requests
to be sent to the data read PLB interface (data from caching inhibited locations will not be reused from the
DCLFD buffer).
The DCC includes three DCLFD buffers, such that a total of three independent data cache line fill requests
can be in progress at one time. The DCC can continue to process subsequent load and store accesses while
these line fills are in progress.
The DCC also includes a 4-entry load miss queue (LMQ), which holds up to four outstanding load instructions
that have either missed in the data cache or access caching inhibited memory pages. Collectively, any LMQ
entries which reference cacheable memory pages can reference no more than three different cache lines,
since there are only three DCLFD buffers. A load instruction in the LMQ remains there until the requested
data arrives in the DCLFD buffer, at which time the data is delivered to the register file and the instruction is
removed from the LMQ.