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TCR
Timer Control Register
Preliminary PPC440x5 CPU Core User’s Manual
regsumm440core.fm.
September 12, 2002 Page 515 of 589
TCR
SPR 0x154 Supervisor R/W
See Timer Control Register (TCR) on page 215.
Figure 10-47. Timer Control Register (TCR)
0:1 WP
Watchdog Timer Period
00 2
21
time base clocks
01 2
25
time base clocks
10 2
29
time base clocks
11 2
33
time base clocks
2:3 WRC
Watchdog Timer Reset Control
00 No Watchdog Timer reset will occur.
01 Core reset
10 Chip reset
11 System reset
TCR[WRC] resets to 0b00.
Type of reset to cause upon Watchdog Timer excep-
tion with TSR[ENW,WIS]=0b11.
This field can be set by software, but cannot be
cleared by software, except by a software-induced
reset.
4 WIE
Watchdog Timer Interrupt Enable
0 Disable Watchdog Timer interrupt.
1 Enable Watchdog Timer interrupt.
5
DIE
Decrementer Interrupt Enable
0 Disable Decrementer interrupt.
1 Enable Decrementer interrupt.
6:7 FP
Fixed Interval Timer (FIT) Period
00 2
13
time base clocks
01 2
17
time base clocks
10 2
21
time base clocks
11 2
25
time base clocks
8 FIE
FIT Interrupt Enable
0 Disable Fixed Interval Timer interrupt.
1 Enable Fixed Interval Timer interrupt.
9 ARE
Auto-Reload Enable
0 Disable auto reload.
1 Enable auto reload.
TCR[ARE] resets to 0b0.
10:31 Reserved
012345678910 31
WP
WRC
WIE
DIE
FP FIE
ARE