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User’s Manual
PPC440x5 CPU Core Preliminary
Page 220 of 589
debug.fm.
September 12, 2002
page 159 for a description of the MSR and Debug interrupts). When a Debug interrupt occurs, special
debugger software at the interrupt handler can check processor status and other conditions related to the
debug event, as well as alter processor resources using all of the instructions defined for the PPC440x5.
Internal debug mode relies on this interrupt handling software at the Debug interrupt vector to debug software
problems. This mode, used while the processor executes instructions, enables debugging of both application
programs and operating system software, including all of the non-critical class interrupt handlers.
In this mode, the debugger software can communicate with the outside world through a communications port,
such as a serial port, external to the processor core.
To enable internal debug mode, the IDM field of DBCR0 must be set to 1 (DBCR0[IDM] = 1). This mode can
be enabled in combination with external debug mode (see External Debug Mode below) and/or debug wait
mode (see Debug Wait Mode on page 220).
8.2.2 External Debug Mode
External debug mode provides access to architected processor resources and supports stopping, starting,
and stepping the processor, setting hardware and software breakpoints, and monitoring processor status. In
this mode, debug events record their status in the DBSR and then cause the processor to enter the stop
state, in which normal instruction execution stops and architected processor resources and memory can be
accessed and altered via the JTAG interface. While in the stop state, interrupts are temporarily disabled.
Storage access control by a memory management unit (MMU) remains in effect while in external debug
mode; the debugger may need to modify MSR or TLB values to access protected memory.
External debug mode relies only on internal processor resources, and no Debug interrupt handling software,
so it can be used to debug both system hardware and software problems. This mode can also be used for
software development on systems without a control program, or to debug control program problems,
including problems within the Debug interrupt handler itself, or within any other critical class interrupt
handlers.
External debug mode is enabled by setting DBCR0[EDM] to 1. This mode can be enabled in combination with
internal debug mode (see Internal Debug Mode on page 219) and/or debug wait mode (see Debug Wait
Mode below). External debug mode takes precedence over internal debug mode however, in that debug
events will first cause the processor to enter stop state rather than generating a Debug interrupt, although a
Debug interrupt may be pending while the processor is in the stop state.
8.2.3 Debug Wait Mode
Debug wait mode is similar to external debug mode in that debug events cause the processor to enter the
stop state. However, interrupts are still enabled while in debug wait mode, such that if and when an exception
occurs for which the associated interrupt type is enabled, the processor will leave the stop state and generate
the interrupt. This mode is useful for real-time hardware environments which cannot tolerate interrupts being
disabled for an extended period of time. In such environments, if external debug mode were to be used,
various I/O devices could operate incorrectly due to not being serviced in a timely fashion when they assert
an interrupt request to the processor, if the processor happened to be in stop state at the time of the interrupt
request.
When in debug wait mode, as with external debug mode, access to the architected processor resources and
memory is via the JTAG interface.