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User’s Manual
Preliminary PPC440x5 CPU Core
instalfa.fm.
September 12, 2002
Page 537 of 589
cmpwi
[BF,] RA, IM
Compare Word Immediate.
UseCR[CR0] if BF is omitted.
Extended mnemonic for
cmpi BF,0,RA,IM
283
cntlzw
RA, RS
Count leading zeros in RS.
Place result in RA.
286
cntlzw.
CR[CR0]
crand
BT, BA, BB
AND bit (CR
BA
) with (CR
BB
).
Place result in CR
BT
.
287
crandc
BT, BA, BB
AND bit (CR
BA
) with ¬(CR
BB
).
Place result in CR
BT
.
288
crclr
bx
Condition register clear.
Extended mnemonic for
crxor bx,bx,bx
294
creqv
BT, BA, BB
Equivalence of bit CR
BA
with CR
BB
.
CR
BT
←¬(CR
BA
⊕ CR
BB
)
289
crmove
bx, by
Condition register move.
Extended mnemonic for
cror bx,by,by
292
crnand
BT, BA, BB
NAND bit (CR
BA
) with (CR
BB
).
Place result in CR
BT
.
290
crnor
BT, BA, BB
NOR bit (CR
BA
) with (CR
BB
).
Place result in CR
BT
.
291
crnot
bx, by
Condition register not.
Extended mnemonic for
crnor bx,by,by
291
cror
BT, BA, BB
OR bit (CR
BA
) with (CR
BB
).
Place result in CR
BT
.
292
crorc
BT, BA, BB
OR bit (CR
BA
) with ¬(CR
BB
).
Place result in CR
BT
.
293
crset
bx
Condition register set.
Extended mnemonic for
creqv bx,bx,bx
289
crxor
BT, BA, BB
XOR bit (CR
BA
) with (CR
BB
).
Place result in CR
BT
.
294
dcba
RA, RB Treated as a no-op. 295
dcbf
RA, RB
Flush (store, then invalidate) the data cache block which con-
tains the effective address (RA|0) + (RB).
296
dcbi
RA, RB
Invalidate the data cache block which contains the effective
address (RA|0) + (RB).
297
dcbst
RA, RB
Store the data cache block which contains the effective address
(RA|0) + (RB).
298
dcbt
RA, RB
Load the data cache block which contains the effective address
(RA|0) + (RB).
299
dcbtst
RA,RB
Load the data cache block which contains the effective address
(RA|0) + (RB).
300
dcbz
RA, RB
Zero the data cache block which contains the effective address
(RA|0) + (RB).
302
dccci
RA, RB Invalidate the data cache array. 304
Table A-1. PPC440x5 Instruction Syntax Summary (continued)
Mnemonic Operands Function
Other Registers
Changed
Page