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DBCR2 (cont.)
Debug Control Register 2
PPC440x5 CPU Core User’s Manual Preliminary
Page 474 of 589
regsumm440core.fm.
September 12, 2002
14:15 DVC2M
DVC 2 Mode
00 Reserved
01 AND all bytes enabled by DVC2BE
10 OR all bytes enabled by DVC2BE
11 AND-OR pairs of bytes enabled by DVC2BE
(0 AND 1) OR (2 AND 3)
16:19
Reserved
20:23 DVC1BE DVC 1 Byte Enables 0:3
24:27 Reserved
28:31 DVC2BE DVC 2 Byte Enables 0:3