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tlbre
TLB Read Entry
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 435 of 589
tlbre
TLB Read Entry
tlbentry ← TLB[(RA)
26:31
]
if WS =0
(RT)
0:27
← tlbentry[EPN,V,TS,SIZE]
if CCR0[CRPE] = 0
(RT)
28:31
←
4
0
else
(RT)
28:31
← TPAR
MMUCR[STID]
← tlbentry[TID]
else if WS = 1
(RT)
0:21
← tlbentry[RPN]
if CCR0[CRPE] = 0
(RT)
22:23
←
2
0
else
(RT)
22:23
← PAR1
(RT)
24:27
←
4
0
(RT)
28:31
← tlbentry[ERPN]
else if WS = 2
if CCR0[CRPE] = 0
(RT)
0:1
←
2
0
else
(RT)
0:1
← PAR2
(RT)
2:15
←
14
0
(RT)
16:24
← tlbentry[U0,U1,U2,U3,W,I,M,G,E]
(RT)
25
← 0
(RT)
26:31
← tlbentry[UX,UW,UR,SX,SW,SR]
else (RT), MMUCR[STID]
← undefined
The contents of the specified portion of the selected TLB entry are placed into register RT (and also
MMUCR[STID] if WS = 0).
The parity bits in the TLB entry (TPAR, PAR1, and PAR2) are placed into the register RT if and only if the
Cache Read Parity Enable bit, CCR0[CRPE], is set to 1.
The contents of RA are used as an index into the TLB. If this value is greater than the index of the highest
numbered TLB entry (63), the results are undefined.
The WS field specifies which portion of the TLB entry is placed into RT. If WS = 0, the TID field of the selected
TLB entry is read into MMUCR[STID]. See Memory Management on page 133 for descriptions of the TLB
entry fields.
If the value of the WS field is greater than 2, the instruction form is invalid and the result is undefined.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
tlbre RT, RA, WS
31 RT RA WS 946
0 6 11 16 21 31