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User’s Manual
PPC440x5 CPU Core Preliminary
Page 126 of 589
cache.fm.
September 12, 2002
4.3.3.2 Core Configuration Register 0 (CCR0)
The CCR0 register controls the behavior of the dcbt instruction, the handling of misaligned memory
accesses, and the store gathering mechanism. The CCR0 register also controls various other functions within
the PPC440x5 core that are unrelated to the data cache. Each of these functions is discussed in more detail
in the related sections of this manual.
Figure 4-5 on page 109 illustrates the fields of the CCR0 register.
4.3.3.3 Core Configuration Register 1 (CCR1)
The CCR1 register controls the behavior of the line flushes in response to cast-outs or dcbf or dcbst instruc-
tions. It also contains bits to control the artificial injection of parity errors for software testing purposes. Some
of those bits affect the data cache, while other control the MMU or instruction cache. Each of these functions
is discussed in more detail in the related sections of this manual.
Figure 4-6 on page 110 illustrates the fields of the CCR1 register.
4.3.3.4 dcbt and dcbtst Operation
The dcbt instruction is typically used as a “hint” to the processor that a particular block of data is likely to be
referenced by the executing program in the near future. Thus the processor can begin filling that block into
the data cache, so that when the executing program eventually performs a load from the block it will already
be present in the cache, thereby improving performance.
The dcbtst instruction is typically used for a similar purpose, but specifically for cases where the executing
program is likely to store to the referenced block in the near future. The differentiation in the purpose of the
dcbtst instruction relative to the dcbt instruction is only relevant within shared-memory systems with hard-
ware-enforced support for cache coherency. In such systems, the dcbtst instruction would attempt to estab-
lish the block within the data cache in such a fashion that the processor would most readily be able to
subsequently write to the block (for example, in a processor with a MESI-protocol cache subsystem, the block
might be obtained in Exclusive state). However, because the PPC440x5 core does not provide support for
hardware-enforced cache coherency, the dcbtst instruction is handled in an identical fashion to the dcbt
instruction. The rest of this section thus makes reference only to the dcbt instruction, but in all cases the
information applies to dcbtst as well.
Of course, it would not typically be advantageous if the filling of the cache line requested by the dcbt itself
caused a delay in the reading of data needed by the currently executing program. For this reason, the default
behavior of the dcbt instruction is for it to be ignored if the filling of the requested cache block cannot be
immediately commenced and waiting for such commencement would result in the DCC execution pipeline
being stalled. For example, the dcbt instruction will be ignored if all three DCLFD buffers are already in use,
and execution of subsequent storage access instructions is pending.
On the other hand, the dcbt instruction can also be used as a convenient mechanism for setting up a fixed,
known environment within the data cache. This is useful for establishing contents for cache line locking, or for
deterministic performance on a particular sequence of code, or even for debugging of low-level hardware and
software problems.
When being used for these latter purposes, it is important that the dcbt instruction deliver a deterministic
result, namely the guaranteed establishment in the cache of the specified line. Accordingly, the PPC440x5
core provides a field in the CCR0 register which can be used to cause the dcbt instruction to operate in this
manner. Specifically, when the CCR0 [GDCBT] field is set, the execution of dcbt is guaranteed to establish