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User’s Manual
Preliminary PPC440x5 CPU Core
cache.fm.
September 12, 2002
Page 105 of 589
the ICC will immediately present the request for the new cache line, such that it may be serviced immediately
after the previous cache line read is completed. The ICC never aborts any PLB request once it has been
made, except when a processor reset occurs while the PLB request is being made.
Programming Note:
It is a programming error for an instruction fetch request to reference a valid cache line in the
instruction cache if the caching inhibited storage attribute is set for the memory page containing
the cache line. The result of attempting to execute an instruction from such an access is
undefined. After processor reset, hardware automatically sets the caching inhibited storage
attribute for the memory page containing the reset address, and also automatically flash
invalidates the instruction cache. Subsequently, lines will not be placed into the instruction cache
unless they are accessed by reference to a memory page for which the caching inhibited attribute
has been turned off. If software subsequently turns on the caching inhibited storage attribute for
such a page, software must make sure that no lines from that page remain valid in the instruction
cache, before attempting to fetch and execute instructions from the (now caching inhibited) page.
4.2.2 Speculative Prefetch Mechanism
The ICC can be configured to automatically prefetch up to three more cache lines upon (in addition to the line
being requested by the instruction unit) in response to a cache miss. This speculative prefetch only occurs on
requests for lines from cacheable memory pages, and then only if enabled by the setting of certain fields in
the Core Configuration Register 0 (CCR0) (see Figure 4-5 on page 109).
CCR0[ICSLC] specifies the number of additional cache lines (from 0 to 3) to speculatively prefetch upon an
instruction cache miss. If this field is non-zero, upon an instruction cache miss, the ICC will first check the
cache to see whether the additional lines are themselves already in the cache. If not, then the ICC will
present a fixed-length burst request to the instruction PLB interface, requesting the additional cache line(s).
The burst request is presented after the cache line request for the initial cache line requested by the instruc-
tion unit is presented and acknowledged on the PLB.
The speculative line fill mechanism will not request lines past the end of the minimum memory page size,
which is 1KB. That is, if the line requested by the instruction unit is at or near the end of an aligned 1KB
boundary, the speculative prefetch mechanism will only request those additional lines specified by the
CCR0[ICSLC] field that are also within the same 1KB page of memory. This allows the speculative prefetch
mechanism to operate without having to access the Memory Management Unit (MMU) for a translation for the
next page address.
Another field in the CCR0 register, CCR0[ICSLT], specifies a threshold value that is used to determine
whether the speculative burst request should be abandoned prior to completion, as a result of a change in
direction in the instruction stream (such as a branch or interrupt). If the instruction unit requests a new cache
line and the new request is a hit in the instruction cache, both the original line fill request and any speculative
burst request associated with it will be unaffected. Furthermore, if the new cache line requested by the
instruction unit is a miss in the instruction cache, any prior request which has not yet been requested on the
PLB interface will be cancelled, regardless of the value of CCR0[ICSLT]. However, if a prior speculative burst
request has already been requested on the PLB interface, the value of CCR0[ICSLT] determines if and when
the speculative burst request will be abandoned. CCR0[ICSLT] specifies the number of doublewords (8-byte
units) of the current cache line which must already have been received by the ICC, in order that the filling of
the current cache line will not be abandoned (note that in this context, the term “current” refers to the cache
line with which the next PLB data transfer is associated, at the time that the ICC determines that it needs to
request a new line). That is, if the ICC has already received the number of doublewords indicated by
CCR0[ICSLT], the ICC will not terminate the burst until it has received that entire cache line. All additional