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User’s Manual
PPC440x5 CPU Core Preliminary
Page 28 of 589
overview.fm.
September 12, 2002
• 9-port (6-read, 3-write) 32x32-bit General Purpose Register (GPR) file
• Hardware support for all CPU misaligned accesses
• Full support for both big and little endian byte ordering
• Extensive power management designed into core for maximum performance/power efficiency
• Primary caches
• Independently configurable instruction and data cache arrays
• Array size offerings: 32KB, 16KB, and 8KB
• Single-cycle access
• 32-byte (eight word) line size
• Highly-associative (64-way for 32KB/16KB, 32-way for 8KB)
• Write-back and write-through operation
• Control over whether stores will allocate or write-through on cache miss
• Extensive load/store queues and multiple line fill/flush buffers
• Non-blocking with up to four outstanding load misses
• Cache line locking supported
• Caches can be partitioned to provide separate regions for “transient” instructions and data
• High associativity permits efficient allocation of cache memory
• Critical word first data access and forwarding
• Cache tags and data are parity protected against soft errors.
• Memory Management Unit
• Separate instruction and data shadow TLBs
• 64-entry, fully-associative unified TLB array
• Variable page sizes (1KB-256MB), simultaneously resident in TLB
• 4-bit extended real address for 36-bit (64 GB) addressability
• Flexible TLB management with software page table search
• Storage attibute controls for write-through, caching inhibited, guarded, and byte order (endianness)
• Four user-definable storage attribute controls (for controlling CodePack™ code compression and
transient data, for example)
• TLB tags and data are parity protected against soft errors.
• Debug facilities
• Extensive hardware debug facilities incorporated into the IEEE 1149.1 JTAG port
• Multiple instruction and data address breakpoints (including range)
• Data value compare
• Single-step, branch, trap, and other debug events
• Non-invasive real-time software trace interface
• Timer facilities
– 64-bit time base