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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 205 of 589
This exception will occur if an attached floating-point unit recognizes and supports the instruction, float-
ing-point instruction processing is enabled (MSR[FP]=1), and the instruction sets FPSCR[FEX] to 1.
8. Debug (ICMP exception)
6.7.5 Exception Priorities for Allocated Instructions (Other)
The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of any allocated instruction other than a load or store, and which is
not one of the allocated instructions implemented within the PPC440x5 core.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)
4. Program (Illegal Instruction exception)
This exception will occur if no auxiliary processor unit is attached to the PPC440x5 core, or if the particu-
lar allocated instruction is not recognized by the attached auxiliary processor and is not one of the allo-
cated instructions implemented within the PPC440x5 core.
5. Program (Privileged Instruction exception)
This exception will occur if an attached auxiliary processor unit recognizes the instruction and indicates
that the instruction is privileged, but MSR[PR]=1.
6. Auxiliary Processor Unavailable (Auxiliary Processor Unavailable exception)
This exception will occur if an attached auxiliary processor recognizes the instruction, but indicates that
auxiliary processor instruction processing is disabled (whether or not auxiliary processor instruction pro-
cessing is enabled is implementation-dependent).
7. Program (Unimplemented Operation exception)
This exception will occur if an attached auxiliary processor recognizes but does not support the instruc-
tion, and also indicates that auxiliary processor instruction processing is enabled (whether or not auxiliary
processor instruction processing is enabled is implementation-dependent).
8. Program (Auxiliary Processor Enabled exception)
This exception will occur if an attached auxiliary processor recognizes and supports the instruction, indi-
cates that auxiliary processor instruction processing is enabled, and the instruction execution results in
an Auxiliary Processor Enabled exception. Whether or not auxiliary processor instruction processing is
enabled is implementation-dependent, as is whether or not a given auxiliary processor instruction results
in an Auxiliary Processor Enabled exception.
9. Debug (ICMP exception)
6.7.6 Exception Priorities for Privileged Instructions
The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of any privileged instruction other than dcbi, rfi, rfci, rfmci, or any
allocated instruction not implemented within the PPC440x5 core (all of which are covered elsewhere). This
list does cover, however, the dccci, dcread, iccci, and icread instructions, which are privileged, allocated