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User’s Manual
Preliminary PPC440x5 CPU Core
cache.fm.
September 12, 2002
Page 95 of 589
4. Instruction and Data Caches
The PPC440x5 core provides separate instruction and data cache controllers and arrays, which allow concur-
rent access and minimize pipeline stalls. The storage capacity of the cache arrays, which can range from
8KB–32KB each, depends upon the implementation. Both cache controllers have 32-byte lines, and both are
highly associative, having 64-way set-associativity for 32KB and 16KB sizes, and 32-way set-associativity for
the 8KB size. The PowerPC instruction set provides a rich set of cache management instructions for soft-
ware-enforced coherency. The PPC440x5 implementation also provides special debug instructions that can
directly read the tag and data arrays. The cache controllers interface to the processor local bus (PLB) for
connection to the IBM CoreConnect system-on-a-chip environment.
Both the data and instruction caches are parity protected against soft errors. If such errors are detected, the
CPU will vector to the machine check interrupt handler, where software can take appropriate action. The
details of suggested interrupt handling are described below in section 4.2, “Instruction Cache Controller,” and
in section 4.3, “Data Cache Controller.”
The rest of this chapter provides more detailed information about the operation of the instruction and data
cache controllers and arrays.
4.1 Cache Array Organization and Operation
The instruction and data cache arrays are organized identically, although the fields of the tag and data
portions of the arrays are slightly different because the functions of the arrays differ, and because the instruc-
tion cache is virtually tagged while the data cache has real tags.
The associativity of each cache varies according to its size: the 32KB and 16KB cache sizes are 64-way set-
associative, while the 8KB cache size is 32-way set-associative. Accordingly, the number of “sets” in each
cache varies according to its size: the 32KB cache has 16 sets, while the 16KB and 8KB caches have 8 sets.
Regardless of cache array size, the cache line size is always 32 bytes.
The organization of the cache into “ways” and “sets” is as follows. Using the 32KB cache as an example,
there are 64 ways in each set, with a set consisting of all 64 lines (one line from each way) at which a given
memory location can reside. Conversely, and again using the 32KB cache as an example, there are 16 sets
in each way, with a way consisting of 16 lines (one from each set).
Table 4-1 on page -96 illustrates generically the ways and sets of the cache arrays, for any cache size, while
Table 4-2 on page -96 provides specific values for the parameters used in Table 4-1, for the different cache
sizes. As shown in Table 4-2, the tag field for each line in each way holds the high-order address bits associ-