IBM PPC440X5 Computer Hardware User Manual


 
msync
Memory Synchronize
PPC440x5 CPU Core User’s Manual Preliminary
Page 366 of 589
instrset.fm.
September 12, 2002
msync
Memory Synchronize
The msync instruction guarantees that all instructions initiated by the processor preceding msync will
complete before msync completes, and that no subsequent instructions will be initiated by the processor
until after msync completes. msync also will not complete until all storage accesses associated with instruc-
tions preceding msync have completed.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
None.
Invalid Instruction Forms
Reserved fields
Programming Notes
The msync instruction is execution synchronizing (see Execution Synchronization on page 83), and guaran-
tees that all storage accesses initiated by instructions executed prior to the msync have completed before
any instructions after the msync begin execution. On the other hand, architecturally the mbar instruction
merely orders storage accesses, and does not perform execution synchronization. Therefore, non-storage
access instructions after mbar could complete before the storage access instructions which were executed
prior to mbar have actually completed their storage accesses. However, the PPC440x5 core implements the
mbar instruction identically to the msync instruction, and thus both are execution synchronizing.
Software should nevertheless use the correct instruction (mbar or msync) as called for by the specific
ordering and synchronizing requirements of the application, in order to guarantee portability to other imple-
mentations.
See Storage Ordering and Synchronization on page 84 for additional information on the use of the msync
and mbar instructions.
Architecture Note
mbar replaces the PowerPC eieio instruction. mbar uses the same opcode as eieio; PowerPC applications
which used eieio will get the function of mbar when executed on a PowerPC Book-E implementation. mbar
is architecturally “stronger” than eieio, in that eieio forced separate ordering amongst different categories of
storage accesses, while mbar forces such ordering amongst all storage accesses as a single category.
msync replaces the PowerPC sync instruction. msync uses the same opcode as sync; PowerPC applica-
tions which used sync get the function of msync when executed on a PowerPC Book-E implementation.
msync is architecturally identical to the version of sync specified by an earlier version of the PowerPC archi-
tecture.
msync
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