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User’s Manual
Preliminary PPC440x5 CPU Core
prgmodel.fm.
September 12, 2002
Page 79 of 589
2.7.6 Reset Configuration (RSTCFG)
The read-only RSTCFG register reports the values of certain fields of TLB as supplied at reset.
Access to RSTCFG is privileged.
13 DCUPEI
Data Cache U-bit Parity Error Insert
0 record even parity (normal)
1 record odd parity (simulate parity error)
Controls inversion of parity bit recorded for the U
fields in the data cache.
14 DCMPEI
Data Cache Modified-bit Parity Error Insert
0 record even parity (normal)
1 record odd parity (simulate parity error)
Controls inversion of parity bits recorded for the
modified (dirty) field in the data cache.
15 FCOM
Force Cache Operation Miss
0 normal operation
1 cache ops appear to miss the cache
Force icbt , dcbt, dcbtst, dcbst, dcbf, dcbi, and
dcbz to appear to miss the caches. The intended
use is with icbt and dcbt only, which will fill a dupli-
cate line and allow testing of multi-hit parity errors.
See Section 4.2.4.7 Simulating Instruction Cache
Parity Errors for Software Testing on page 114 and
Figure 4.3.3.7 on page 130.
16:19 MMUPEI
Memory Management Unit Parity Error Insert
0 record even parity (normal)
1 record odd parity (simulate parity error)
Controls inversion of paritybits recordedfor the tag
field in the MMU.
20 FFF
Force Full-line Flush
0 flush only as much data as necessary.
1 always flush entire cache lines
When flushing 32-byte (8-word) lines from the data
cache, normal operation is to write nothing, a dou-
ble word, quad word, or the entire 8-word block to
the memory as required by the dirty bits. This bit
ensures that none or all dirty bits are set so that
either nothing or the entire 8-word block is written
to memory when flushing a line from the data
cache. Refer to Section 4.3.1.4 Line Flush Opera-
tions on page 121.
21:23 Reserved
24 TCS
Timer Clock Select
0 CPU timer advances by one at each rising edge
of the CPU input clock (CPMC440CLOCK).
1 CPU timer advances by one for each rising edge
of the CPU timer clock
(CPMC440TIMERCLOCK).
When TCS = 1, CPU timer clock input can toggle
at up to half of the CPU clock frequency.
25:31 Reserved
Figure 2-13. Reset Configuration
0:15 Reserved
16 U0
U0 Storage Attribute
0 U0 storage attribute is disabled
1 U0 storage attribute is enabled
See Table 5-1 on page 135.
0 15 16 17 18 19 20 23 24 25 27 28 31
U0
U1
U2
U3
E
ERPN