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User’s Manual
Preliminary PPC440x5 CPU Core
cache.fm.
September 12, 2002
Page 125 of 589
4.3.3 Data Cache Control and Debug
The PPC440x5 core provides various registers and instructions to control data cache operation and to help
debug data cache problems.
4.3.3.1 Data Cache Management and Debug Instruction Summary
For detailed descriptions of the instructions summarized in this section, see Instruction Set on page 249
In the instruction descriptions, the term “block” describes the unit of storage operated on by the cache block
instructions. For the PPC440x5 core, this is the same as a cache line.
The following instructions are used by software to manage the data cache.
dcba Data Cache Block Allocate
This instruction is implemented as a nop on the PPC440x5 core.
dcbf Data Cache Block Flush
Writes a cache block to memory (if the block has been modified) and then invalidates the
block.
dcbi Data Cache Block Invalidate
Invalidates a cache block. Any modified data is discarded and not flushed to memory.
Execution of this instruction is privileged.
dcbst Data Cache Block Store
Writes a cache block to memory (if the block has been modified) and leaves the block
valid but marked as unmodified.
dcbt Data Cache Block Touch
Initiates a cache block fill, enabling the fill to begin prior to the executing program
requiring any data in the block. The program can subsequently access the data in the
block without incurring a cache miss.
dcbtst Data Cache Block Touch for Store
Implemented identically to the dcbt instruction.
dcbz Data Cache Block Set to Zero
Establishes a cache line in the data cache and sets the line to all zeros, without first
reading the previous contents of the cache block from memory, thereby improving
performance. All four doublewords in the line are marked as dirty.
dccci Data Cache Congruence Class Invalidate
Flash invalidates the entire data cache. Execution of this instruction is privileged.
dcread Data Cache Read
Reads a cache line (tag and data) from a specified index of the data cache, into a GPR
and a pair of SPRs. Execution of this instruction is privileged.
See dcread Operation on page 127.