Filter
Top Products
User’s Manual
PPC440x5 CPU Core Preliminary
Page 70 of 589
prgmodel.fm.
September 12, 2002
• Certain forms of various integer instructions (the “.” forms) implicitly update CR[CR0], as do certain forms
of the auxiliary processor instructions implemented within the PPC440x5 core.
• Auxiliary processor instructions may in general update a specified CR field in an implementation-speci-
fied manner. In addition, if an auxiliary processor implements the floating-point operations specified by
PowerPC Book-E, then those instructions update the CR in the manner defined by the architecture. See
Book E: PowerPC Architecture Enhanced for Embedded Applications for details.
CR[CR0] Implicit Update By Integer Instructions
Most of the CR-updating instructions listed in Table 2-24 implicitly update the CR0 field. These are the
various “dot-form” instructions, indicated by a “.” in the instruction mnemonic. Most of these instructions
update CR[CR0] according to an arithmetic comparison of 0 with the 32-bit result which the instruction writes
to the GPR file. That is, after performing the operation defined for the instruction, the 32-bit result which is
written to the GPR file is compared to 0 using a signed comparison, independent of whether the actual oper-
ation being performed by the instruction is considered “signed” or not. For example, logical instructions such
as and., or., and nor. update CR[CR0] according to this signed comparison to 0, even though the result of
such a logical operation is not typically interpreted as a signed value. For each of these dot-form instructions,
the individual bits in CR[CR0] are updated as follows:
Note that if an arithmetic overflow occurs, the “sign” of an instruction result indicated in CR[CR0] might not
represent the “true” (infinitely precise) algebraic result of the instruction that set CR0. For example, if an add.
instruction adds two large positive numbers and the magnitude of the result cannot be represented as a twos-
complement number in a 32-bit register, an overflow occurs and CR[CR0]
0
is set, even though the infinitely
precise result of the add is positive.
Similarly, adding the largest 32-bit twos-complement negative number (0x80000000) to itself results in an
arithmetic overflow and 0x0000 0000 is recorded in the target register. CR[CR0]
2
is set, indicating a result of
0, but the infinitely precise result is negative.
CR[CR0]
3
is a copy of XER[SO] at the completion of the instruction, whether or not the instruction which is
updating CR[CR0] is also updating XER[SO]. Note that if an instruction causes an arithmetic overflow but is
not of the form which actually updates XER[SO], then the value placed in CR[CR0]
3
does not reflect the arith-
metic overflow which occurred on the instruction (it is merely a copy of the value of XER[SO] which was
already in the XER before the execution of the instruction updating CR[CR0]).
There are a few dot-form instructions which do not update CR[CR0] in the fashion described above. These
instructions are: stwcx., tlbsx., and dlmzb. See the instruction descriptions in Instruction Set on page 249 for
details on how these instructions update CR[CR0].
CR[CR0]
0
— LT Less than 0; set if the most-significant bit of the 32-bit result is 1.
CR[CR0]
1
— GT Greater than 0; set if the 32-bit result is non-zero and the most-
significant bit of the result is 0.
CR[CR0]
2
— EQ Equal to 0; set if the 32-bit result is 0.
CR[CR0]
3
— SO Summary overflow; a copy of XER[SO] at the completion of the
instruction (including any XER[SO] update being performed the
instruction itself.