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User’s Manual
PPC440x5 CPU Core Preliminary
Page 42 of 589
prgmodel.fm.
September 12, 2002
The 14-bit BD field is concatenated on the right with 0b00, sign-extended, and then added to either the
address of the branch instruction if AA=0, or to 0 if AA=1; the low-order 32 bits of the sum form the effec-
tive address of the next instruction.
• Taken XL-form branch instructions:
The contents of bits 0:29 of the Link Register (LR) or the Count Register (CTR) are concatenated on the
right with 0b00 to form the 32-bit effective address of the next instruction.
• Next sequential instruction fetching (including non-taken branch instructions):
The value 4 is added to the address of the current instruction to form the 32-bit effective address of the
next instruction. If the address of the current instruction is 0xFFFFFFFC, the PPC440x5 core wraps the
next sequential instruction address back to address 0. This behavior is not required by the architecture,
which specifies that the next sequential instruction address is undefined under these circumstances.
Therefore, software should not depend upon this behavior, so that it may be ported to other implementa-
tions that do not handle this scenario in the same fashion. Accordingly, if software wishes to execute
across this maximum address boundary and wrap back to address 0, it should place an unconditional
branch at the boundary, with a displacement of 4.
In addition to the above four instruction storage addressing modes, the following behavior applies to
branch instructions:
• Any branch instruction with LK=1:
The value 4 is added to the address of the current instruction and the low-order 32 bits of the result are
placed into the LR. As for the similar scenario for next sequential instruction fetching, if the address of the
branch instruction is 0xFFFF FFFC, the result placed into the LR is architecturally undefined, although
once again the PPC440x5 core wraps the LR update value back to address 0. Again, however, software
should not depend on this behavior, in order that it may be ported to implementations which do not han-
dle this scenario in the same fashion.
2.1.3 Byte Ordering
If scalars (individual data items and instructions) were indivisible, there would be no such concept as “byte
ordering.” It is meaningless to consider the order of bits or groups of bits within the smallest addressable unit
of storage, because nothing can be observed about such order. Only when scalars, which the programmer
and processor regard as indivisible quantities, can comprise more than one addressable unit of storage does
the question of order arise.
For a machine in which the smallest addressable unit of storage is the 64-bit doubleword, there is no question
of the ordering of bytes within doublewords. All transfers of individual scalars between registers and storage
are of doublewords, and the address of the byte containing the high-order eight bits of a scalar is no different
from the address of a byte containing any other part of the scalar.
For the Book-E Enhanced PowerPC Architecture, as for most current computer architectures, the smallest
addressable unit of storage is the 8-bit byte. Many scalars are halfwords, words, or doublewords, which
consist of groups of bytes. When a word-length scalar is moved from a register to storage, the scalar occu-
pies four consecutive byte addresses. It thus becomes meaningful to discuss the order of the byte addresses
with respect to the value of the scalar: which byte contains the highest-order eight bits of the scalar, which
byte contains the next-highest-order eight bits, and so on.
Given a scalar that contains multiple bytes, the choice of byte ordering is essentially arbitrary. There are 4! =
24 ways to specify the ordering of four bytes within a word, but only two of these orderings are sensible: