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User’s Manual
Preliminary PPC440x5 CPU Core
overview.fm.
September 12, 2002
Page 27 of 589
1. Overview
The IBM™ PowerPC™ 440x5 32-bit embedded processor core, referred to as the PPC440x5 core, imple-
ments the Book-E Enhanced PowerPC Architecture.
This chapter describes:
• PPC440x5 core features
• The PPC440x5 core as an implementation of the Book-E Enhanced PowerPC Architecture
• The organization of the PPC440x5 core, including a block diagram and descriptions of the functional units
• PPC440x5 core interfaces
1.1 PPC440x5 Features
The PPC440x5 core is a high-performance, low-power engine that implements the flexible and powerful
Book-E Enhanced PowerPC Architecture.
The PPC440x5 contains a dual-issue, superscalar, pipelined processing unit, along with other functional
elements required by embedded ASIC product specifications. These other functions include memory
management, cache control, timers, and debug facilities. Interfaces for custom co-processors and floating
point functions are provided, along with separate instruction and data cache array interfaces which can be
configured to various sizes (optimized for 32KB). The processor local bus (PLB) system interface has been
extended to 128 bitsand is fully compatible with the IBM CoreConnect on-chip system architecture, providing
the framework to efficiently support system-on-a-chip (SOC) designs.
In addition, the PPC440x5 core is a member of the PowerPC 400 Series of advanced embedded processors
cores, which is supported by the PowerPC Embedded Tools Program. In this program, IBM and many third-
party vendors offer a full range of robust development tools for embedded applications. Among these are
compilers, debuggers, real-time operating systems, and logic analyzers.
PPC440x5 features include:
• High performance, dual-issue, superscalar 32-bit RISC CPU
• Superscalar implementation of the full 32-bit Book-E Enhanced PowerPC Architecture
• Seven stage, highly-pipelined micro-architecture
• Dual instruction fetch, decode, and out-of-order issue
• Out-of-order dispatch, execution, and completion
• High-accuracy dynamic branch prediction using a Branch History Table (BHT)
• Reduced branch latency using Branch Target Address Cache (BTAC)
• Three independent pipelines
• Combined complex integer, system, and branch pipeline
• Simple integer pipeline
• Load/store pipeline
• Single cycle multiply
• Single cycle multiply-accumulate (DSP instruction set extensions)