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User’s Manual
Preliminary PPC440x5 CPU Core
init.fm.
September 12, 2002
Page 89 of 589
3.2 Reset Types
The PPC440x5 core supports three types of reset: core, chip, and system. The type of reset is indicated by a
set of core input signals. For each type of reset, the core resources are initialized as indicated in Table 3-1 on
page 86. Core reset is intended to reset the PPC440x5 core without necessarily resetting the rest of the on-
chip logic. The chip reset operation is intended to reset the entire chip, but off-chip hardware in the system is
not informed of the reset operation. System reset is intended to reset the entire chip, and also to signal the
rest of the off-chip system that the chip is being reset.
3.3 Reset Sources
A reset operation can be initiated on the PPC440x5 core through the use of any of four separate mecha-
nisms. The first is a set of three input signals to the core, one for each of the three reset types. These signals
can be asserted asynchronously by hardware outside the core to initiate a reset operation. The second reset
source is the TCR[WRC] field, which can be setup by software to initiate a reset operation upon certain
Watchdog Timer expiration events. The third reset source is the DBCR0[RST] field, which can be written by
software to immediately initiate a reset operation. The fourth reset source is the JTAG interface, which can be
used by a JTAG-attached debug tool to initiate a reset operation asynchronously to program execution on the
PPC440x5 core.
3.4 Initialization Software Requirements
After a reset operation occurs, the PPC440x5 core is initialized to a minimum configuration to enable the
fetching and execution of the software initialization code, and to guarantee deterministic behavior of the core
during the execution of this code. Initialization software is necessary to complete the configuration of the
processor core and the rest of the on-chip and off-chip system.
The system must provide non-volatile memory (or memory initialized by some mechanism other than the
PPC440x5 core) at the real address corresponding to effective address 0xFFFFFFFC, and at the rest of the
initial program memory page. The instruction at the initial address must be an unconditional branch back-
wards to the beginning of the initialization software sequence.
The initialization software functions described in this section perform the configuration tasks required to
prepare the PPC440x5 core to boot an operating system and subsequently execute an application program.
The initialization software must also perform functions associated with hardware resources that are outside
the PPC440x5 core, and hence that are beyond the scope of this manual. This section makes reference to
some of these functions, but their full scope is described in the user’s manual for the specific chip and/or
system implementation.
Initialization software should perform the following tasks in order to fully configure the PPC440x5 core. For
more information on the various functions referenced in the initialization sequence, see the corresponding
chapters of this document.
1. Branch backwards from effective address 0xFFFFFFFC to the start of the initialization sequence