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User’s Manual
PPC440x5 CPU Core Preliminary
Page 196 of 589
intrupts.fm.
September 12, 2002
specified by the various debug facility registers. This exception can occur regardless of
debug mode, and regardless of the value of MSR[DE].
Branch Taken (BRT) exception
A BRT Debug exception occurs when BRT debug events are enabled (DBCR0[BRT]=1) and
execution is attempted of a branch instruction for which the branch conditions are met. This
exception cannot occur in internal debug mode when MSR[DE]=0, unless external debug
mode or debug wait mode is also enabled.
Trap (TRAP) exception
A TRAP Debug exception occurs when TRAP debug events are enabled (DBCR0[TRAP]=1)
and execution is attempted of a tw or twi instruction that matches any of the specified trap
conditions. This exception can occur regardless of debug mode, and regardless of the value
of MSR[DE].
Return (RET) exception
A RET Debug exception occurs when RET debug events are enabled (DBCR0[RET]=1) and
execution is attempted of an
rfi, rfci, or rfmci instruction. For rfi, the RET Debug exception
can occur regardless of debug mode and regardless of the value of MSR[DE]. For rfci
or
rfmci, the RET Debug exception cannot occur in internal debug mode when MSR[DE]=0,
unless external debug mode or debug wait mode is also enabled.
Instruction Complete (ICMP) exception
An ICMP Debug exception occurs when ICMP debug events are enabled (DBCR0[ICMP]=1)
and execution of any instruction is completed. This exception cannot occur in internal debug
mode when MSR[DE]=0, unless external debug mode or debug wait mode is also enabled.
Interrupt (IRPT) exception
An IRPT Debug exception occurs when IRPT debug events are enabled (DBCR0[IRPT]=1)
and an interrupt occurs. For non-critical class interrupt types, the IRPT Debug exception can
occur regardless of debug mode and regardless of the value of MSR[DE]. For critical class
interrupt types, the IRPT Debug exception cannot occur in internal debug mode (regardless
of the value of MSR[DE]), unless external debug mode or debug wait mode is also enabled.
Unconditional Debug Event (UDE) exception
A UDE Debug exception occurs when an Unconditional Debug Event is signaled over the
JTAG interface to the PPC440x5 core. This exception can occur regardless of debug mode,
and regardless of the value of MSR[DE].
There are four debug modes supported by the PPC440x5 core. They are: internal debug mode, external
debug mode, debug wait mode, and trace mode. Debug exceptions and interrupts are affected by the debug
mode(s) which are enabled at the time of the Debug exception. Debug interrupts occur only when internal
debug mode is enabled, although it is possible for external debug mode and/or debug wait mode to be
enabled as well. The remainder of this section assumes that internal debug mode is enabled and that
external debug mode and debug wait mode are not enabled, at the time of a Debug exception.
See Chapter 8, “Debug Facilities” for more information on the different debug modes and the behavior of
each of the Debug exception types when operating in each of the modes.