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User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5LOF.fm.
September 12, 2002
Page 17 of 583
Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL) .............................................................479
Figure 10-15. Data Exception Address Register (DEAR) ...........................................................................480
Figure 10-16. Decrementer (DEC) .............................................................................................................481
Figure 10-17. Decrementer Auto-Reload (DECAR) ...................................................................................482
Figure 10-18. Data Cache Normal Victim Registers (DNV0–DNV3) ..........................................................483
Figure 10-19. Data Cache Transient Victim Registers (DTV0–DTV3) .......................................................484
Figure 10-20. Data Value Compare Registers (DVC1–DVC2) ...................................................................485
Figure 10-21. Data Cache Victim Limit (DVLIM) ........................................................................................486
Figure 10-22. Exception Syndrome Register (ESR) ...................................................................................487
Figure 10-23. General Purpose Registers (R0-R31) ..................................................................................489
Figure 10-24. Instruction Address Compare Registers (IAC1–IAC4) .........................................................490
Figure 10-25. Instruction Cache Debug Data Register (ICDBDR) .............................................................491
Figure 10-26. Instruction Cache Debug Tag Register High (ICDBTRH) ....................................................492
Figure 10-27. Instruction Cache Debug Tag Register Low (ICDBTRL) ......................................................493
Figure 10-28. Instruction Cache Normal Victim Registers (INV0–INV3) ....................................................494
Figure 10-29. Instruction Cache Transient Victim Registers (ITV0–ITV3) ..................................................495
Figure 10-30. Instruction Cache Victim Limit (IVLIM) .................................................................................496
Figure 10-31. Interrupt Vector Offset Registers (IVOR0–IVOR15) ............................................................497
Figure 10-32. Interrupt Vector Prefix Register (IVPR) ................................................................................498
Figure 10-33. Link Register (LR) ................................................................................................................499
Figure 10-34. Machine Check Status Register (MCSR) .............................................................................500
Figure 10-35. Machine Check Save/Restore Register 0 (MCSRR0) ..........................................................501
Figure 0-2. Machine Check Save/Restore Register 1 (MCSRR1) ..........................................................502
Figure 10-36. Memory Management Unit Control Register (MMUCR) .......................................................503
Figure 10-37. Machine State Register (MSR) ............................................................................................504
Figure 10-38. Process ID (PID) ..................................................................................................................506
Figure 10-39. Processor Identification Register (PIR) ................................................................................507
Figure 10-40. Processor Version Register (PVR) .......................................................................................508
Figure 10-41. Reset Configuration .............................................................................................................509
Figure 10-42. Special Purpose Registers General (SPRG0–SPRG7) .......................................................510
Figure 10-43. Save/Restore Register 0 (SRR0) .........................................................................................511
Figure 10-44. Save/Restore Register 1 (SRR1) .........................................................................................512
Figure 10-45. Time Base Lower (TBL) .......................................................................................................513
Figure 10-46. Time Base Upper (TBU) .......................................................................................................514
Figure 10-47. Timer Control Register (TCR) ..............................................................................................515
Figure 10-48. Timer Status Register (TSR) ................................................................................................516
Figure 10-49. User Special Purpose Register General (USPRG0) ............................................................517
Figure 10-50. Integer Exception Register (XER) ........................................................................................518
Figure A-1. I Instruction Format ..............................................................................................................522