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User’s Manual
PPC440x5 CPU Core Preliminary
Page 16 of 583
ppc440x5LOF.fm.
September 12, 2002
Figure 6-3. Save/Restore Register 1 (SRR1) .........................................................................................168
Figure 6-4. Critical Save/Restore Register 0 (CSRR0) ...........................................................................168
Figure 6-5. Critical Save/Restore Register 1 (CSRR1) ...........................................................................169
Figure 6-6. Machine Check Save/Restore Register 0 (MCSRR0) ..........................................................169
Figure 0-1. Machine Check Save/Restore Register 1 (MCSRR1) ..........................................................170
Figure 6-7. Data Exception Address Register (DEAR) ...........................................................................170
Figure 6-8. Interrupt Vector Offset Registers (IVOR0–IVOR15) ............................................................171
Figure 6-9. Interrupt Vector Prefix Register (IVPR) ................................................................................172
Figure 6-10. Exception Syndrome Register (ESR) ...................................................................................172
Figure 6-11. Machine Check Status Register (MCSR) .............................................................................174
Figure 7-1. Relationship of Timer Facilities to the Time Base ................................................................209
Figure 7-2. Time Base Lower (TBL) ........................................................................................................210
Figure 7-3. Time Base Upper (TBU) .......................................................................................................210
Figure 7-4. Decrementer (DEC) ..............................................................................................................211
Figure 7-5. Decrementer Auto-Reload (DECAR) ....................................................................................212
Figure 7-6. Watchdog State Machine .....................................................................................................215
Figure 7-7. Timer Control Register (TCR) ...............................................................................................216
Figure 7-8. Timer Status Register (TSR) ................................................................................................217
Figure 8-1. Debug Control Register 0 (DBCR0) .....................................................................................239
Figure 8-2. Debug Control Register 1 (DBCR1) .....................................................................................240
Figure 8-3. Debug Control Register 2 (DBCR2) .....................................................................................243
Figure 8-4. Debug Status Register (DBSR) ............................................................................................244
Figure 8-5. Instruction Address Compare Registers (IAC1–IAC4) .........................................................246
Figure 8-6. Data Address Compare Registers (DAC1–DAC2) ...............................................................246
Figure 8-7. Data Value Compare Registers (DVC1–DVC2) ...................................................................246
Figure 8-8. Debug Data Register (DBDR) ..............................................................................................247
Figure 10-1. Core Configuration Register 0 (CCR0) .................................................................................460
Figure 10-2. Core Configuration Register 1 (CCR1) .................................................................................462
Figure 10-3. Condition Register (CR) .......................................................................................................464
Figure 10-4. Critical Save/Restore Register 0 (CSRR0) ...........................................................................465
Figure 10-5. Critical Save/Restore Register 1 (CSRR1) ...........................................................................466
Figure 10-6. Count Register (CTR) ...........................................................................................................467
Figure 10-7. Data Address Compare Registers (DAC1–DAC2) ...............................................................468
Figure 10-8. Debug Control Register 0 (DBCR0) .....................................................................................469
Figure 10-9. Debug Control Register 1 (DBCR1) .....................................................................................471
Figure 10-10. Debug Control Register 2 (DBCR2) .....................................................................................473
Figure 10-11. Debug Data Register (DBDR) ..............................................................................................475
Figure 10-12. Debug Status Register (DBSR) ............................................................................................476
Figure 10-13. Data Cache Debug Tag Register High (DCDBTRH) ............................................................478