Filter
Top Products
User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 181 of 589
See Machine Check Interrupts on page 161 for more information on the handling of Machine Check interrupts
within the PPC440x5 core.
Programming Note: If a Instruction Synchronous Machine Check exception occurs (i.e.
an error occurs on the PLB transfer that is intended to fill a line in the
instruction cache, any data associated with the exception will not be
placed into the instruction cache. On the other hand, if a Data
Asynchronous Machine Check exception occurs due to a PLB error
during a cacheable read operation, the data associated with the
exception will be placed into the data cache, and could subsequently
be loaded into a register. Similarly, if a Data Asynchronous Machine
Check exception due to a PLB error occurs during a caching inhibited
read operation, the data associated with the exception will be read into
a register. Data Asynchronous Machine Check exceptions resulting
from parity errors may or may not corrupt a GPR value, depending on
the setting of the CCR0[PRE] field. See Data Cache Parity Operations
on page 129.
Programming Note: Since a dcbz instruction establishes a real address in the data cache
without actually reading the block of data from memory, it is possible
for a delayed Data Machine Check exception to occur if and when a
line established by a dcbz instruction is cast-out of the data cache and
written to memory, if the address of the cache line is not valid within
the system implementation.
6.5.3 Data Storage Interrupt
A Data Storage interrupt may occur when no higher priority exception exists and a Data Storage exception is
presented to the interrupt mechanism. The PPC440x5 core includes four types of Data Storage exception.
They are:
Read Access Control exception
A Read Access Control exception is caused by one of the following:
• While in user mode (MSR[PR] = 1), a load, icbi, icbt, dcbst, dcbf, dcbt, or dcbtst instruction
attempts to access a location in storage that is not enabled for read access in user mode (that is, the
TLB entry associated with the memory page being accessed has UR=0).
• While in supervisor mode (MSR[PR] = 0), a load, icbi, icbt, dcbst, dcbf, dcbt, or dcbtst instruction
attempts to access a location in storage that is not enabled for read access in supervisor mode (that
is, the TLB entry associated with the memory page being accessed has SR=0).
Programming Note: The instruction cache management instructions icbi and icbt are
treated as “loads” from the addressed byte with respect to address
translation and protection. These instruction cache management
instructions use MSR[DS] rather than MSR[IS] to determine
translation for their target effective address. Similarly, they use the
read access control field (UR or SR) rather than the execute access
control field (UX or SX) of the TLB entry to determine whether a Data
Storage exception should occur. Instruction Storage exceptions and
Instruction TLB Miss exceptions are associated with the fetching of