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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 207 of 589
6.7.9 Exception Priorities for Branch Instructions
The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of a branch instruction.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)
4. Debug (BRT exception)
5. Debug (ICMP exception)
6.7.10 Exception Priorities for Return From Interrupt Instructions
The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of an rfi, rfci, or rfmci instruction.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)
4. Debug (RET exception)
5. Debug (ICMP exception)
6.7.11 Exception Priorities for Preserved Instructions
The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of a preserved instruction.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)
4. Program (Illegal Instruction exception)
Applies to all preserved instructions except the mftb instruction, which is the only preserved class
instruction implemented within the PPC440x5 core.
5. Debug (ICMP exception)
Only applies to the mftb instruction, which is the only preserved class instruction implemented within the
PPC440x5 core.
6.7.12 Exception Priorities for Reserved Instructions
The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of a reserved instruction.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)