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User’s Manual
PPC440x5 CPU Core Preliminary
Page 4 of 583
ppc440x5TOC.fm.
September 12, 2002
2.3.2 Allocated Instruction Class ..................................................................................................... 54
2.3.3 Preserved Instruction Class ................................................................................................... 55
2.3.4 Reserved Instruction Class .................................................................................................... 56
2.4 Implemented Instruction Set Summary ........................................................................................... 56
2.4.1 Integer Instructions ................................................................................................................ 57
2.4.1.1 Integer Storage Access Instructions ............................................................................... 57
2.4.1.2 Integer Arithmetic Instructions ........................................................................................ 58
2.4.1.3 Integer Logical Instructions ............................................................................................. 59
2.4.1.4 Integer Compare Instructions ......................................................................................... 59
2.4.1.5 Integer Trap Instructions ................................................................................................. 59
2.4.1.6 Integer Rotate Instructions ............................................................................................. 59
2.4.1.7 Integer Shift Instructions ................................................................................................. 60
2.4.1.8 Integer Select Instruction ................................................................................................ 60
2.4.2 Branch Instructions ................................................................................................................ 60
2.4.3 Processor Control Instructions ............................................................................................... 60
2.4.3.1 Condition Register Logical Instructions .......................................................................... 61
2.4.3.2 Register Management Instructions ................................................................................. 61
2.4.3.3 System Linkage Instructions ........................................................................................... 61
2.4.3.4 Processor Synchronization Instruction ........................................................................... 61
2.4.4 Storage Control Instructions .................................................................................................. 62
2.4.4.1 Cache Management Instructions .................................................................................... 62
2.4.4.2 TLB Management Instructions ........................................................................................ 62
2.4.4.3 Storage Synchronization Instructions ............................................................................. 63
2.4.5 Allocated Instructions ............................................................................................................. 63
2.5 Branch Processing .......................................................................................................................... 64
2.5.1 Branch Addressing ................................................................................................................. 64
2.5.2 Branch Instruction BI Field ..................................................................................................... 64
2.5.3 Branch Instruction BO Field ................................................................................................... 64
2.5.4 Branch Prediction ................................................................................................................... 65
2.5.5 Branch Control Registers ....................................................................................................... 66
2.5.5.1 Link Register (LR) ........................................................................................................... 66
2.5.5.2 Count Register (CTR) ..................................................................................................... 67
2.5.5.3 Condition Register (CR) ................................................................................................. 67
2.6 Integer Processing .......................................................................................................................... 71
2.6.1 General Purpose Registers (GPRs) ....................................................................................... 71
2.6.2 Integer Exception Register (XER) .......................................................................................... 72
2.6.2.1 Summary Overflow (SO) Field ........................................................................................ 73
2.6.2.2 Overflow (OV) Field ........................................................................................................ 74
2.6.2.3 Carry (CA) Field .............................................................................................................. 74
2.7 Processor Control ............................................................................................................................ 74
2.7.1 Special Purpose Registers General (USPRG0, SPRG0–SPRG7) ........................................ 75
2.7.2 Processor Version Register (PVR) ........................................................................................ 75
2.7.3 Processor Identification Register (PIR) .................................................................................. 76
2.7.4 Core Configuration Register 0 (CCR0) .................................................................................. 76
2.7.5 Core Configuration Register 1 (CCR1) .................................................................................. 78
2.7.6 Reset Configuration (RSTCFG) ............................................................................................. 79
2.8 User and Supervisor Modes ............................................................................................................ 80
2.8.1 Privileged Instructions ............................................................................................................ 80
2.8.2 Privileged SPRs ..................................................................................................................... 81
2.9 Speculative Accesses ..................................................................................................................... 81